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Example pcieboot_helloworld in L2SRAM

Marek Wisnia
Prodigy 140 points

Hello all,


The example mcsdk_2_01_02_06\tools\boot_loader\examples\pcie\pcieboot_helloworld
wokrs well under CCS when program is located in DDR or MSM, but
Core1-Core7 do not wake up when program is located in L2SRAM.

Could somebody give the example where Core0 wakes up Core1-Core7
and the same program's code is located in the corresponding CorePak's L2SRAM ?

Thank you a priori,

I used MDSEVM6678L+MDXEVMPCI boards, CCS 5.2.1.00018, mcsdk_2_01_02_06.

Best regards,
Marek

  • 0
    TI__Mastermind 28085 points
    Hi,

    DDR and MSMC are common memory for all cores, all core(0-7) able to access this memory location and boot properly. But L2SRAM is a specific corepac memory, specific core only able to access this memory location and boot it. Ex: 0x10800000 to 0x1087FFFF region is CorePac0 L2 SRAM memory, core0 only able to access this memory region.

    Thanks,
  • 0 in reply to Ganapathi Dhandapani95
    Prodigy 140 points

    Hi,

    Core0 can write to the CorePakN L2 SPRAM directly.
    E.g. with the function
    memcpy((void*)(0x1N800000), (void*)0x00800000, 0x50000);

    Program code can be copied from Core0 to the CorePakN L2 SRAM
    with the memcopy.
    Then necessary to initialize the MAGIC_BOOT_ADDRESSes of Core1-Core7
    and to send IPC interrupt for Core1-Core7.
    Example pcieboot_helloworld does these operations.
    I added memcpy to this program, then set
    .text > L2SRAM in the *.cmd file.
    And modified program waked up the Core1-Core7.
    So as I thing I have got the modified program example for all the Cores
    working in L2SRAM under CCS.

    Interesting thing - I still can not get right result
    for the TI's pcieboot_helloworld example loaded from Linux host.
    Core1-Core7 do not wake up there.

    Thank you,

    Best regards,
    Marek

  • 0 in reply to Marek Wisnia
    TI__Mastermind 28085 points
    Hi,

    The Linux host first pushes the DDR init boot image data to L2 memory of core 0, then writes the boot entry address of the DDR init boot image to the magic address on core 0, both via PCIE. When the EVM is in PCIE boot mode, the IBL code running on the DSP core 0 polls the entry address and jumps to that address and starts to boot (initialize the DDR). After DDR is properly
    initialized, the DDR init code clears the magic address and keeps on polling it.
    Linux host then pushes the HelloWorld boot image data to DDR memory, then writes the boot entry address of the HelloWorld boot image to the magic address on core 0 to boot core 0. Core 0 starts to boot and print the “Hello World” booting information, and then boot all the other cores by writing the address of _c_int00 to the magic address on other cores and sending an IPC
    interrupt to other cores. The RBL running on other cores will jump to _c_int00 and start to boot.

    Have you modified the Linux host demo example to push the test code image to L2 memory of all cores?
    Have you check the Core1-Core7 L2SRAM memory after image write? Default TI example use common DDR memory to boot all the cores.

    Thanks,
  • 0 in reply to Ganapathi Dhandapani95
    Prodigy 140 points

    Hi,

    >Have you modified the Linux host demo example...?
    No...
    Yes!
    I turned on local reset
    #define LOCAL_RESET 1
    and forgot about it. This was the cause.

    All the cores wake up now with the Linux host image loading.

    Thank you very much!

    Best regards,
    Marek

  • 0 in reply to Marek Wisnia
    TI__Mastermind 28085 points
    Thanks for your update. It will be useful for other community members.