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6657 Core 1 interrupt handler problem

Ilan Bogen
Intellectual 330 points
Other Parts Discussed in Thread: TMS320C6655

Hi,

I wrote an interrupt handler for a Timer Interrupt and a handler for a PCIe legacy and I used it while running in Core 0.

When I ran the same code on Core 1 I didn't reach the ISR.

What can be the reason?

Thanks,

Ilan.

  • 0
    TI__Guru* 81335 points
    The Timer 0 interrupt can not be received in Core1. Please refer the "Interrupt Event" table in specific device data manual. Similarly check the interrupt configuration for PCIe legacy interrupt routing with keystone interrupts manual.

    Refer below wiki for how the system interrupts are routed to Core PAC interrupt controller.

    processors.wiki.ti.com/.../Configuring_Interrupts_on_Keystone_Devices

    Thank you.
  • 0
    TI__Mastermind 28085 points

    Hi,

    TImer 0 and Timer 1 are corepac timers. Timer 0 map to core 0 and timer 1 map to core 1, user not able to re-configure this timer to other corepacs. Refer DSP data manual for more information.

    CorePac[n] will receive TINTLn and TINTHn.

    Thanks,

  • 0 in reply to Ganapathi Dhandapani95
    Intellectual 330 points
    Hi,

    Thanks for the clarification.

    So, I would like to be sure, Timer 0 interrupt is connected to CorePac0 and Timer 1 interrupt is connected to CorePac1, and both share the same Event Number- 64, right?

    What about PCIEXpress_Legacy_INTA, event number 50 in CIC0 Event Inputs.
    Does it trigger both CorePacs, 0 and 1?

    Thanks,
    Ilan.
  • 0 in reply to Ilan Bogen
    TI__Mastermind 28085 points

    Hi,

    So, I would like to be sure, Timer 0 interrupt is connected to CorePac0 and Timer 1 interrupt is connected to CorePac1, and both share the same Event Number- 64, right?

    Yes, your understanding is correct. Timer2 and Timer3 interrupts are not specified to CorePac's, user can configure this interrupt for any CorePac's.

    What about PCIEXpress_Legacy_INTA, event number 50 in CIC0 Event Inputs.

    Does it trigger both CorePacs, 0 and 1?

    Based on your configuration, CIC0 Event to System Event Interrupt Controller output configuration. For example, If you map  PCIEXpress_Legacy_INTA, event number 50 to System Event Interrupt Controller output CIC0_OUT(0+20*n) event number 22 means specific CorePac only receive the interrupt.

    Note: n is core number.

    Thanks,

  • 0 in reply to Ganapathi Dhandapani95
    Intellectual 330 points
    Hi,

    I thought I understood it, but still I need some more clarification.

    Can one input event be map to the cores.

    Eg. PCIEXpress_Legacy_INTA, input event number 50 to System Event Interrupt Controller output CIC0_OUT(0) event number 22 and CIC0_OUT(20) event number 22.

    How does the CIC0 transfer event number 22 to both cores ?
    Is it done automatically or should some setting take place to transfer it to Core0 or Core1?

    Thanks,
    Ilan.
  • 0 in reply to Ilan Bogen
    TI__Guru* 81335 points
    For Broadcasting events, you can select event number 56- 63 from Table 7-33 TMS320C6655/57 System Event Mapping.
    For Core specfic events, you can select event number 22-31, 92, 93 from Table 7-33 TMS320C6655/57 System Event Mapping.

    For example,
    Event 22 on the C66 core is connected to CIC out 0+ 20 * N, that is
    Core 0 event 22 is connected to CIC output event 0
    Core 1 event 22 is connected to CIC output event 20

    Please refer Hyperlink interrupt example availble in MCSDK for more information. Thank you.
  • 0 in reply to Ilan Bogen
    TI__Mastermind 28085 points
    Hi,

    Raja example is correct for CIC OUT mapping to corepac's.
    Eg. PCIEXpress_Legacy_INTA, input event number 50 to System Event Interrupt Controller output CIC0_OUT(0) event number 22 and CIC0_OUT(20) event number 22. If you run the same code on all cores means, each core will get the interrupt.

    For core 0, CIC input event event 22 is connected to CIC output event 0 and interrupt to core 0 only.
    For core 1, CIC input event 22 is connected to CIC output event 20 and interrupt to core 1 only.

    Thanks,
  • 0 in reply to Ganapathi Dhandapani95
    Intellectual 330 points

    Hi,

    In my code PCIEXpress_Legacy_INTA, input event number 50 is mapped to event number 25.

    System Event Interrupt Controller output CIC0_OUT(3) or CIC0_OUT(23)

    After initilization  I see the following setting on both cores:
    EVTMASK0 - Address 0x01800080  - value =0x0200000F    ==> event number 25 is masked
    INTMUX1    - Address 0x01800104   - value =0x00001519    ==> event number 25 is selected

    After triggering PCIEXpress_Legacy_INTA  I see the following:

    On Core0  EVTFLAG0 - Address 0x01800000 - Value 0x02000008 ==> Flag 25 is set
    On Core1  EVTFLAG0 - Address 0x01800000 - Value 0x00000008  ==> Flag 25 is not set

    It seems that core1 doesn't get the event.

    Does the input event mapping split automatically to the two cores as CIC0_OUT(3) and CIC0_OUT(23) ?

    Or is there any other setting to the CIC0 to tell it to map to Core1 also?

    Thanks,

    Ilan.

  • 0 in reply to Ilan Bogen
    TI__Mastermind 28085 points

    Hi,

    Have you using C6657 DSP for your testing? If yes, CIC0_OUT40 to CIC0_OUT47 Interrupt Controller Output only connected to all corepac's. Better to use this Interrupt Controller Output mapped to event number 56-63. Example: PCIEXpress_Legacy_INTA, input event number 50 is mapped to event number 56.

    Refer attached Interrupt training document. 7356.3326.KeyStone_Interrupts.pptx

    Thanks,