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C6670 EVM SRIO in Line Loopback

Hari..
Intellectual 605 points

Hi,

I am trying to implement SRIO_LoopbackTestProject (pdk_C6670_1_1_2_6\packages\ti\drv\exampleProjects\SRIO_LoopbackTestProject) in board to board scenario.

Board Setup:


EVM6670LE  Board A  --> TI LC Dual EVM Breakout card  --> EVM6670LE  Board B


I want to send data from EVM board A and do line loopback on EVM board B to transmit the received data.

For this I changed the code in device_srio_loopback.c file to put the EVM A in normal mode as shown below and loaded the .out file in EVM A.

   /* Configure SRIO ports to operate in loopback mode.
    CSL_SRIO_SetLoopbackMode(hSrio, 0);
    CSL_SRIO_SetLoopbackMode(hSrio, 1);
    CSL_SRIO_SetLoopbackMode(hSrio, 2);
    CSL_SRIO_SetLoopbackMode(hSrio, 3); */

    /* Configure SRIO to operate in Normal mode. */
    CSL_SRIO_SetNormalMode (hSrio,0);
    CSL_SRIO_SetNormalMode (hSrio,1);
    CSL_SRIO_SetNormalMode (hSrio,2);
    CSL_SRIO_SetNormalMode (hSrio,3);

I have problem in configuring the EVM B in line loopback mode.


1. How do I put the EVM in line loopback mode. Is it just enabling the LLB bit in PLM_SP(n)_IMP_SPEC_CTL register as shown below ?

    // Bypass the tx clock crossing the FIFO
    implControl.lineLoopbackMode = 1;
    CSL_SRIO_SetPLMPortImplSpecificControl (hSrio, 0, &implControl);
    CSL_SRIO_SetPLMPortImplSpecificControl (hSrio, 1, &implControl);
    CSL_SRIO_SetPLMPortImplSpecificControl (hSrio, 2, &implControl);
    CSL_SRIO_SetPLMPortImplSpecificControl (hSrio, 3, &implControl); */

2. Do I need to do anything else other than adding the above code in the device_srio_loopback.c file  to get the .out file for EVM board B ? I mean do I need to remove any part of the code that was in project for Board A (Data transfer code or initialization code) ?

Can someone help me with this.

Thanks

Hari

  • 0
    TI__Mastermind 28085 points

    Hi,

    Please take a look at MCSDK SRIO Throughput test code. It support multiple modes internal/external loopback, normal board to board mode and external SRIO switch.

    MCSDK Path: C:\ti\pdk_C6678_1_1_2_6\packages\ti\drv\exampleProjects\SRIO_TputBenchmarkingTestProject

    Refer SRIO_Benchmarking_Example_Code_Guide document, it will help you modify a test code for multiple modes.

    Doc Path: \ti\pdk_C6678_1_1_2_6\packages\ti\drv\srio\test\tput_benchmarking\docs\SRIO_Benchmarking_Example_Code_Guide

    SMA connections are looped back for each of the SRIO ports on the breakout card. If external line loopback is enabled, data received on RX “line” will be directly send back to TX “line”. Refer section 2.6.3 External line loopback on SRIO Programming and Performance Data document. 6825.SRIO_Programming_Performance.pdf

    Refer below SRIO line loopback threads to configure the line loopback on your EVMB.

    Thanks,

  • 0
    TI__Mastermind 23525 points
    Yes, you would have to put both EVM A and B in normal mode, then enable the line loopback in EVM B. I think you are doing that part correct. However, the difficulty that you will run into is that there is no clock compensation and you have to use the same clock source on both devices. This is not possible using two EVMs. You also have to use SRIO traffic, no other traffic including PRBS can be used.

    Regards,
    Travis
  • 0 in reply to tscheck
    Intellectual 605 points
    Travis,

    Thank you ..!! I have few more questions.

    1. So is it not possible to do line loopback using two EVMs ?
    2. And when you say clock compensation what does that exactly mean ? Is it extracting the clock from the data stream in the SERDES clock recovery block ?
    3. What would be the working setup for line loop back ?
    4. If c6670 gets data from FPGA over SRIO lane how do I loopback the data on 6670 and re-transmit back to FPGA ?

    Thanks
    Hari
  • 0 in reply to Hari..
    TI__Mastermind 23525 points
    1) correct
    2) Serdes do the clock recovery, but not the compensation if the reference clocks on both ends of the link are not locked there will be drift. This can not be tolerated in the line loopback case.
    3)Two devices on the same board with the same ref clock.
    4) If the C6670 doesn't actually regenerate the packets completely, then you'd have to use the line loopback.

    Travis
  • 0 in reply to tscheck
    Intellectual 605 points
    Thank you. So if there is a drift in the clock where would that effect ? Is the re-transmission not done on the receive side (EVM B loop back) or the data will be re-transmitted but not received on EVM A ?

    Hari
  • 0 in reply to Hari..
    TI__Mastermind 23525 points
    What comes out of EVM B would be junk, and depending on how bad the drift is, EVM A might not even be able to sync on the RapidIO protocol and establish port_ok. Hard to tell, it could show up as bit errors only.