We have designed our custom SBC based on Advantech EVM XTCIEVMK2X and using 6638K2H12 SOC. We are in the process of constraining our layout for the second time.
According to DDR3 guidlines DDR3 Design Requirements for KeyStone Devices May 2014, the min skew between "Coomand delay" and "data delay" on any SDRAM must meet a MIN delay of 325 ps. Looking at the advantech EVM we see the routing violates this requirement As we see approximately a delay of 144 ps. Yet the eval board seems to work fine. We need assistance for our layout constraints, as this is our second attempt.