This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Haw to speed up file reading from host

Other Parts Discussed in Thread: TMS320C6678

Hi all,
How can I speed up read data file into character format from host? I have data size of 1700 Kbytes. I spend reading this file about 300 sec. I use TMS320C6678 with Blackhawk XDS560v2 - USB Mezzanine Emulator and CCS v5.2 and Windows 7
My code is

while(fgets(_buf, sizeof(_buf), pfile)) {
_buf[strlen(_buf)-1] = '\0';
value = atof(_buf);
. . . . 

I don't use Ethernet into this project. I don't use any OS on board DSP. It is requirement of my customers. This project used to rigorously prove the correctness of the existence and stability of solution. 
Best reagards,
   Oleg

PS this is my own project, no example. I make initialization of environment (DDR, timer and other) without GEL file

  • Hi Oleg,

    Are you talking about the speed of the emulator?? or you are talking about the performance of the standard library functions such as fopen(), fread(), fwrite() etc?

    If it is about the Standard library functions, you can try out someother functions for file operations. There are lot of file operation APIs.

    If it is about the emulator speed, please try adaptive clocking.

    Try whether it is possible to have adaptive clocking in XDS for better performance and speed in downloading from host.

    processors.wiki.ti.com/.../Adaptive_Clocking
    processors.wiki.ti.com/.../XDS_Target_Connection_Guide

    ---

  • I've looked into this once (though on another board and with on-board jtag interface) and my assessment was following. It should help to increase buffer size, but increasing its maximum size involves modification and recompilation of corresponding rts*.lib. At the same time there was no guarantee that it would have worked, because limit could be hard-coded into CSS in which case attempt to use larger .cio buffer would have devastating effect . So I've never actually attempted it, because it was for a short experiment, and I reckoned that I can afford wasting couple of hours waiting for I/O instead of venturing into rts*.lib recompilation. If you feel that rts*.lib recompilation is worth the try for you, then increasing BUFSIZ in stdio.h appears to be sufficient, but you really have to recompile everything from scratch. As you seem to be running bare-metal, it should be feasible...

    For reference. I/O to/from host triggers break-point (at C$$IO$$), which is served by CCS by copying data  to/from .cio segment. This is high-overhead operation and I find it hard to believe that adhering to alternative interface (fgets vs. read) would make much of a difference. Well, it might make some, but not impressively much, because overhead is there in either case and is overwhelming. Note that fgets does use buffer (by default), so that it's not like it pulls data from host byte by byte...

  • Hi Shankari,
    I tried use the video from processors.wiki.ti.com/.../Adaptive_Clocking
    as pattern for Adaptive Clocking. I have next results (I beg your pardon, I have to be
    somewhat verbose)
    My first result - all fields Default (Fields JTAG TCLKFrequency (MHz) and
    TMS/TDO Output Timing)


    [Start]

    Execute the command:

    %ccs_base%/common/uscif/dbgjtag.exe -f %boarddatafile% -rv -o -F inform,logfile=yes -S pathlength -S integrity

    [Result]


    -----[Print the board config pathname(s)]------------------------------------

    C:\Users\BOROVI~1\AppData\Local\.TI\693494126\
    0\0\BrdDat\testBoard.dat

    -----[Print the reset-command software log-file]-----------------------------

    This utility has selected a 560/2xx-class product.
    This utility will load the program 'bh560v2u.out'.
    Loaded FPGA Image: C:\ti\ccsv5\ccs_base\common\uscif\dtc_top.jbc
    The library build date was 'Aug 19 2013'.
    The library build time was '22:41:20'.
    The library package version is '5.1.229.0'.
    The library component version is '35.34.40.0'.
    The controller does not use a programmable FPGA.
    The controller has a version number of '5' (0x00000005).
    The controller has an insertion length of '0' (0x00000000).
    The cable+pod has a version number of '8' (0x00000008).
    The cable+pod has a capability number of '7423' (0x00001cff).
    This utility will attempt to reset the controller.
    This utility has successfully reset the controller.

    -----[Print the reset-command hardware log-file]-----------------------------

    The scan-path will be reset by toggling the JTAG TRST signal.
    The controller is the Nano-TBC VHDL.
    The link is a 560-class second-generation-560 cable.
    The software is configured for Nano-TBC VHDL features.
    The controller will be software reset via its registers.
    The controller has a logic ONE on its EMU[0] input pin.
    The controller has a logic ONE on its EMU[1] input pin.
    The controller will use rising-edge timing on output pins.
    The controller cannot control the timing on input pins.
    The scan-path link-delay has been set to exactly '2' (0x0002).
    The utility logic has not previously detected a power-loss.
    The utility logic is not currently detecting a power-loss.
    Loaded FPGA Image: C:\ti\ccsv5\ccs_base\common\uscif\dtc_top.jbc

    -----[The log-file for the JTAG TCLK output generated from the PLL]----------

    Test Size Coord MHz Flag Result Description
    ~~~~ ~~~~ ~~~~~~~ ~~~~~~~~ ~~~~ ~~~~~~~~~~~ ~~~~~~~~~~~~~~~~~~~
    1 none - 01 00 500.0kHz - similar isit internal clock
    2 none - 01 09 570.3kHz - similar isit internal clock
    3 512 - 01 00 500.0kHz O good value measure path length
    4 128 - 01 00 500.0kHz O good value auto step initial
    5 128 - 01 0D 601.6kHz O good value auto step delta
    6 128 - 01 1C 718.8kHz O good value auto step delta
    7 128 - 01 2E 859.4kHz O good value auto step delta
    8 128 + 00 02 1.031MHz {?} bad value auto step delta
    9 512 - 01 22 765.6kHz O good value auto power initial
    10 512 - 01 32 890.6kHz O good value auto power delta
    11 512 - 01 3A 953.1kHz O good value auto power delta
    12 512 - 01 3E 984.4kHz O good value auto power delta
    13 512 + 00 00 1.000MHz ? bad value auto power delta
    14 512 - 01 3F 992.2kHz O good value auto power delta
    15 512 - 01 3F 992.2kHz O good value auto power delta
    16 512 - 01 32 890.6kHz {O} good value auto margin initial

    The first internal/external clock test resuts are:
    The expect frequency was 500000Hz.
    The actual frequency was 499110Hz.
    The delta frequency was 890Hz.

    The second internal/external clock test resuts are:
    The expect frequency was 570312Hz.
    The actual frequency was 569976Hz.
    The delta frequency was 336Hz.

    In the scan-path tests:
    The test length was 16384 bits.
    The JTAG IR length was 6 bits.
    The JTAG DR length was 1 bits.

    The IR/DR scan-path tests used 16 frequencies.
    The IR/DR scan-path tests used 500.0kHz as the initial frequency.
    The IR/DR scan-path tests used 1.031MHz as the highest frequency.
    The IR/DR scan-path tests used 890.6kHz as the final frequency.

    -----[Measure the source and frequency of the final JTAG TCLKR input]--------

    The frequency of the JTAG TCLKR input is measured as 890.0kHz.

    The frequency of the JTAG TCLKR input and TCLKO output signals are similar.
    The target system likely uses the TCLKO output from the emulator PLL.

    -----[Perform the standard path-length test on the JTAG IR and DR]-----------

    This path-length test uses blocks of 512 32-bit words.

    The test for the JTAG IR instruction path-length succeeded.
    The JTAG IR instruction path-length is 6 bits.

    The test for the JTAG DR bypass path-length succeeded.
    The JTAG DR bypass path-length is 1 bits.

    -----[Perform the Integrity scan-test on the JTAG IR]------------------------

    This test will use blocks of 512 32-bit words.
    This test will be applied just once.

    Do a test using 0xFFFFFFFF.
    Scan tests: 1, skipped: 0, failed: 0
    Do a test using 0x00000000.
    Scan tests: 2, skipped: 0, failed: 0
    Do a test using 0xFE03E0E2.
    Scan tests: 3, skipped: 0, failed: 0
    Do a test using 0x01FC1F1D.
    Scan tests: 4, skipped: 0, failed: 0
    Do a test using 0x5533CCAA.
    Scan tests: 5, skipped: 0, failed: 0
    Do a test using 0xAACC3355.
    Scan tests: 6, skipped: 0, failed: 0
    All of the values were scanned correctly.

    The JTAG IR Integrity scan-test has succeeded.

    -----[Perform the Integrity scan-test on the JTAG DR]------------------------

    This test will use blocks of 512 32-bit words.
    This test will be applied just once.

    Do a test using 0xFFFFFFFF.
    Scan tests: 1, skipped: 0, failed: 0
    Do a test using 0x00000000.
    Scan tests: 2, skipped: 0, failed: 0
    Do a test using 0xFE03E0E2.
    Scan tests: 3, skipped: 0, failed: 0
    Do a test using 0x01FC1F1D.
    Scan tests: 4, skipped: 0, failed: 0
    Do a test using 0x5533CCAA.
    Scan tests: 5, skipped: 0, failed: 0
    Do a test using 0xAACC3355.
    Scan tests: 6, skipped: 0, failed: 0
    All of the values were scanned correctly.

    The JTAG DR Integrity scan-test has succeeded.

    [End]

    The result of a slightly different on pattern - I have the other emulator(Blackhawck XDS560v2 USB Mezzanine Emulator, and
    other version CCSv5.2, but I was confused next
    16 512 - 01 32 890.6kHz {O} good value auto margin initial

    The IR/DR scan-path tests used 890.6kHz as the final frequency.

    As I understand my really frequency clocking is 890.6kHz? Is it true?

    I did next experiment as to video, but my emulator to worked only
    Fields
    JTAG TCLKFrequency (MHz) - Fixed with user specified faster value
    --Enter a value from 0.5MHz to 64MHz 0.5MHz
    TMS/TDS Output Timing Failed edge is JTAG standart
    (any value send to error) - result bellow
    [Start]

    Execute the command:

    %ccs_base%/common/uscif/dbgjtag.exe -f %boarddatafile% -rv -o -F inform,logfile=yes -S pathlength -S integrity

    [Result]


    -----[Print the board config pathname(s)]------------------------------------

    C:\Users\BOROVI~1\AppData\Local\.TI\693494126\
    0\0\BrdDat\testBoard.dat

    -----[Print the reset-command software log-file]-----------------------------

    This utility has selected a 560/2xx-class product.
    This utility will load the program 'bh560v2u.out'.
    Loaded FPGA Image: C:\ti\ccsv5\ccs_base\common\uscif\dtc_top.jbc
    The library build date was 'Aug 19 2013'.
    The library build time was '22:41:20'.
    The library package version is '5.1.229.0'.
    The library component version is '35.34.40.0'.
    The controller does not use a programmable FPGA.
    The controller has a version number of '5' (0x00000005).
    The controller has an insertion length of '0' (0x00000000).
    The cable+pod has a version number of '8' (0x00000008).
    The cable+pod has a capability number of '7423' (0x00001cff).
    This utility will attempt to reset the controller.
    This utility has successfully reset the controller.

    -----[Print the reset-command hardware log-file]-----------------------------

    The scan-path will be reset by toggling the JTAG TRST signal.
    The controller is the Nano-TBC VHDL.
    The link is a 560-class second-generation-560 cable.
    The software is configured for Nano-TBC VHDL features.
    The controller will be software reset via its registers.
    The controller has a logic ONE on its EMU[0] input pin.
    The controller has a logic ONE on its EMU[1] input pin.
    The controller will use falling-edge timing on output pins.
    The controller cannot control the timing on input pins.
    The scan-path link-delay has been set to exactly '2' (0x0002).
    The utility logic has not previously detected a power-loss.
    The utility logic is not currently detecting a power-loss.
    Loaded FPGA Image: C:\ti\ccsv5\ccs_base\common\uscif\dtc_top.jbc

    -----[The log-file for the JTAG TCLK output generated from the PLL]----------

    Test Size Coord MHz Flag Result Description
    ~~~~ ~~~~ ~~~~~~~ ~~~~~~~~ ~~~~ ~~~~~~~~~~~ ~~~~~~~~~~~~~~~~~~~
    1 none - 01 00 500.0kHz - similar isit internal clock
    2 none - 01 09 570.3kHz {-} similar isit internal clock
    3 512 - 01 00 500.0kHz O good value measure path length
    4 512 - 01 00 500.0kHz {O} good value apply explicit tclk

    The first internal/external clock test resuts are:
    The expect frequency was 500000Hz.
    The actual frequency was 499110Hz.
    The delta frequency was 890Hz.

    The second internal/external clock test resuts are:
    The expect frequency was 570312Hz.
    The actual frequency was 569214Hz.
    The delta frequency was 1098Hz.

    In the scan-path tests:
    The test length was 16384 bits.
    The JTAG IR length was 6 bits.
    The JTAG DR length was 1 bits.

    The IR/DR scan-path tests used 4 frequencies.
    The IR/DR scan-path tests used 500.0kHz as the initial frequency.
    The IR/DR scan-path tests used 570.3kHz as the highest frequency.
    The IR/DR scan-path tests used 500.0kHz as the final frequency.

    -----[Measure the source and frequency of the final JTAG TCLKR input]--------

    The frequency of the JTAG TCLKR input is measured as 499.1kHz.

    The frequency of the JTAG TCLKR input and TCLKO output signals are similar.
    The target system likely uses the TCLKO output from the emulator PLL.

    -----[Perform the standard path-length test on the JTAG IR and DR]-----------

    This path-length test uses blocks of 512 32-bit words.

    The test for the JTAG IR instruction path-length succeeded.
    The JTAG IR instruction path-length is 6 bits.

    The test for the JTAG DR bypass path-length succeeded.
    The JTAG DR bypass path-length is 1 bits.

    -----[Perform the Integrity scan-test on the JTAG IR]------------------------

    This test will use blocks of 512 32-bit words.
    This test will be applied just once.

    Do a test using 0xFFFFFFFF.
    Scan tests: 1, skipped: 0, failed: 0
    Do a test using 0x00000000.
    Scan tests: 2, skipped: 0, failed: 0
    Do a test using 0xFE03E0E2.
    Scan tests: 3, skipped: 0, failed: 0
    Do a test using 0x01FC1F1D.
    Scan tests: 4, skipped: 0, failed: 0
    Do a test using 0x5533CCAA.
    Scan tests: 5, skipped: 0, failed: 0
    Do a test using 0xAACC3355.
    Scan tests: 6, skipped: 0, failed: 0
    All of the values were scanned correctly.

    The JTAG IR Integrity scan-test has succeeded.

    -----[Perform the Integrity scan-test on the JTAG DR]------------------------

    This test will use blocks of 512 32-bit words.
    This test will be applied just once.

    Do a test using 0xFFFFFFFF.
    Scan tests: 1, skipped: 0, failed: 0
    Do a test using 0x00000000.
    Scan tests: 2, skipped: 0, failed: 0
    Do a test using 0xFE03E0E2.
    Scan tests: 3, skipped: 0, failed: 0
    Do a test using 0x01FC1F1D.
    Scan tests: 4, skipped: 0, failed: 0
    Do a test using 0x5533CCAA.
    Scan tests: 5, skipped: 0, failed: 0
    Do a test using 0xAACC3355.
    Scan tests: 6, skipped: 0, failed: 0
    All of the values were scanned correctly.

    The JTAG DR Integrity scan-test has succeeded.

    TMS/TDO Output Timing)

    line
    4 512 - 01 00 500.0kHz {O} good value apply explicit tclk
    and
    The IR/DR scan-path tests used 500.0kHz as the final frequency.
    as I expected - final frequency low
    It's all what I did. I can't rise final frequency - max is 890.6kHz - as default

    Best regards
    Oleg

  • Hi Shankari,
    I tried use the video from processors.wiki.ti.com/.../Adaptive_Clocking
    as pattern for Adaptive Clocking. I have next results (I beg your pardon, I have to be
    somewhat verbose)
    My first result - all fields Default (Fields JTAG TCLKFrequency (MHz) and
    TMS/TDO Output Timing)


    [Start]

    Execute the command:

    %ccs_base%/common/uscif/dbgjtag.exe -f %boarddatafile% -rv -o -F inform,logfile=yes -S pathlength -S integrity

    [Result]


    -----[Print the board config pathname(s)]------------------------------------

    C:\Users\BOROVI~1\AppData\Local\.TI\693494126\
    0\0\BrdDat\testBoard.dat

    -----[Print the reset-command software log-file]-----------------------------

    This utility has selected a 560/2xx-class product.
    This utility will load the program 'bh560v2u.out'.
    Loaded FPGA Image: C:\ti\ccsv5\ccs_base\common\uscif\dtc_top.jbc
    The library build date was 'Aug 19 2013'.
    The library build time was '22:41:20'.
    The library package version is '5.1.229.0'.
    The library component version is '35.34.40.0'.
    The controller does not use a programmable FPGA.
    The controller has a version number of '5' (0x00000005).
    The controller has an insertion length of '0' (0x00000000).
    The cable+pod has a version number of '8' (0x00000008).
    The cable+pod has a capability number of '7423' (0x00001cff).
    This utility will attempt to reset the controller.
    This utility has successfully reset the controller.

    -----[Print the reset-command hardware log-file]-----------------------------

    The scan-path will be reset by toggling the JTAG TRST signal.
    The controller is the Nano-TBC VHDL.
    The link is a 560-class second-generation-560 cable.
    The software is configured for Nano-TBC VHDL features.
    The controller will be software reset via its registers.
    The controller has a logic ONE on its EMU[0] input pin.
    The controller has a logic ONE on its EMU[1] input pin.
    The controller will use rising-edge timing on output pins.
    The controller cannot control the timing on input pins.
    The scan-path link-delay has been set to exactly '2' (0x0002).
    The utility logic has not previously detected a power-loss.
    The utility logic is not currently detecting a power-loss.
    Loaded FPGA Image: C:\ti\ccsv5\ccs_base\common\uscif\dtc_top.jbc

    -----[The log-file for the JTAG TCLK output generated from the PLL]----------

    Test Size Coord MHz Flag Result Description
    ~~~~ ~~~~ ~~~~~~~ ~~~~~~~~ ~~~~ ~~~~~~~~~~~ ~~~~~~~~~~~~~~~~~~~
    1 none - 01 00 500.0kHz - similar isit internal clock
    2 none - 01 09 570.3kHz - similar isit internal clock
    3 512 - 01 00 500.0kHz O good value measure path length
    4 128 - 01 00 500.0kHz O good value auto step initial
    5 128 - 01 0D 601.6kHz O good value auto step delta
    6 128 - 01 1C 718.8kHz O good value auto step delta
    7 128 - 01 2E 859.4kHz O good value auto step delta
    8 128 + 00 02 1.031MHz {?} bad value auto step delta
    9 512 - 01 22 765.6kHz O good value auto power initial
    10 512 - 01 32 890.6kHz O good value auto power delta
    11 512 - 01 3A 953.1kHz O good value auto power delta
    12 512 - 01 3E 984.4kHz O good value auto power delta
    13 512 + 00 00 1.000MHz ? bad value auto power delta
    14 512 - 01 3F 992.2kHz O good value auto power delta
    15 512 - 01 3F 992.2kHz O good value auto power delta
    16 512 - 01 32 890.6kHz {O} good value auto margin initial

    The first internal/external clock test resuts are:
    The expect frequency was 500000Hz.
    The actual frequency was 499110Hz.
    The delta frequency was 890Hz.

    The second internal/external clock test resuts are:
    The expect frequency was 570312Hz.
    The actual frequency was 569976Hz.
    The delta frequency was 336Hz.

    In the scan-path tests:
    The test length was 16384 bits.
    The JTAG IR length was 6 bits.
    The JTAG DR length was 1 bits.

    The IR/DR scan-path tests used 16 frequencies.
    The IR/DR scan-path tests used 500.0kHz as the initial frequency.
    The IR/DR scan-path tests used 1.031MHz as the highest frequency.
    The IR/DR scan-path tests used 890.6kHz as the final frequency.

    -----[Measure the source and frequency of the final JTAG TCLKR input]--------

    The frequency of the JTAG TCLKR input is measured as 890.0kHz.

    The frequency of the JTAG TCLKR input and TCLKO output signals are similar.
    The target system likely uses the TCLKO output from the emulator PLL.

    -----[Perform the standard path-length test on the JTAG IR and DR]-----------

    This path-length test uses blocks of 512 32-bit words.

    The test for the JTAG IR instruction path-length succeeded.
    The JTAG IR instruction path-length is 6 bits.

    The test for the JTAG DR bypass path-length succeeded.
    The JTAG DR bypass path-length is 1 bits.

    -----[Perform the Integrity scan-test on the JTAG IR]------------------------

    This test will use blocks of 512 32-bit words.
    This test will be applied just once.

    Do a test using 0xFFFFFFFF.
    Scan tests: 1, skipped: 0, failed: 0
    Do a test using 0x00000000.
    Scan tests: 2, skipped: 0, failed: 0
    Do a test using 0xFE03E0E2.
    Scan tests: 3, skipped: 0, failed: 0
    Do a test using 0x01FC1F1D.
    Scan tests: 4, skipped: 0, failed: 0
    Do a test using 0x5533CCAA.
    Scan tests: 5, skipped: 0, failed: 0
    Do a test using 0xAACC3355.
    Scan tests: 6, skipped: 0, failed: 0
    All of the values were scanned correctly.

    The JTAG IR Integrity scan-test has succeeded.

    -----[Perform the Integrity scan-test on the JTAG DR]------------------------

    This test will use blocks of 512 32-bit words.
    This test will be applied just once.

    Do a test using 0xFFFFFFFF.
    Scan tests: 1, skipped: 0, failed: 0
    Do a test using 0x00000000.
    Scan tests: 2, skipped: 0, failed: 0
    Do a test using 0xFE03E0E2.
    Scan tests: 3, skipped: 0, failed: 0
    Do a test using 0x01FC1F1D.
    Scan tests: 4, skipped: 0, failed: 0
    Do a test using 0x5533CCAA.
    Scan tests: 5, skipped: 0, failed: 0
    Do a test using 0xAACC3355.
    Scan tests: 6, skipped: 0, failed: 0
    All of the values were scanned correctly.

    The JTAG DR Integrity scan-test has succeeded.

    [End]

    The result of a slightly different on pattern - I have the other emulator(Blackhawck XDS560v2 USB Mezzanine Emulator, and
    other version CCSv5.2, but I was confused next
    16 512 - 01 32 890.6kHz {O} good value auto margin initial

    The IR/DR scan-path tests used 890.6kHz as the final frequency.

    As I understand my really frequency clocking is 890.6kHz? Is it true?

    I did next experiment as to video, but my emulator to worked only
    Fields
    JTAG TCLKFrequency (MHz) - Fixed with user specified faster value
    --Enter a value from 0.5MHz to 64MHz 0.5MHz
    TMS/TDS Output Timing Failed edge is JTAG standart
    (any value send to error) - result bellow
    [Start]

    Execute the command:

    %ccs_base%/common/uscif/dbgjtag.exe -f %boarddatafile% -rv -o -F inform,logfile=yes -S pathlength -S integrity

    [Result]


    -----[Print the board config pathname(s)]------------------------------------

    C:\Users\BOROVI~1\AppData\Local\.TI\693494126\
    0\0\BrdDat\testBoard.dat

    -----[Print the reset-command software log-file]-----------------------------

    This utility has selected a 560/2xx-class product.
    This utility will load the program 'bh560v2u.out'.
    Loaded FPGA Image: C:\ti\ccsv5\ccs_base\common\uscif\dtc_top.jbc
    The library build date was 'Aug 19 2013'.
    The library build time was '22:41:20'.
    The library package version is '5.1.229.0'.
    The library component version is '35.34.40.0'.
    The controller does not use a programmable FPGA.
    The controller has a version number of '5' (0x00000005).
    The controller has an insertion length of '0' (0x00000000).
    The cable+pod has a version number of '8' (0x00000008).
    The cable+pod has a capability number of '7423' (0x00001cff).
    This utility will attempt to reset the controller.
    This utility has successfully reset the controller.

    -----[Print the reset-command hardware log-file]-----------------------------

    The scan-path will be reset by toggling the JTAG TRST signal.
    The controller is the Nano-TBC VHDL.
    The link is a 560-class second-generation-560 cable.
    The software is configured for Nano-TBC VHDL features.
    The controller will be software reset via its registers.
    The controller has a logic ONE on its EMU[0] input pin.
    The controller has a logic ONE on its EMU[1] input pin.
    The controller will use falling-edge timing on output pins.
    The controller cannot control the timing on input pins.
    The scan-path link-delay has been set to exactly '2' (0x0002).
    The utility logic has not previously detected a power-loss.
    The utility logic is not currently detecting a power-loss.
    Loaded FPGA Image: C:\ti\ccsv5\ccs_base\common\uscif\dtc_top.jbc

    -----[The log-file for the JTAG TCLK output generated from the PLL]----------

    Test Size Coord MHz Flag Result Description
    ~~~~ ~~~~ ~~~~~~~ ~~~~~~~~ ~~~~ ~~~~~~~~~~~ ~~~~~~~~~~~~~~~~~~~
    1 none - 01 00 500.0kHz - similar isit internal clock
    2 none - 01 09 570.3kHz {-} similar isit internal clock
    3 512 - 01 00 500.0kHz O good value measure path length
    4 512 - 01 00 500.0kHz {O} good value apply explicit tclk

    The first internal/external clock test resuts are:
    The expect frequency was 500000Hz.
    The actual frequency was 499110Hz.
    The delta frequency was 890Hz.

    The second internal/external clock test resuts are:
    The expect frequency was 570312Hz.
    The actual frequency was 569214Hz.
    The delta frequency was 1098Hz.

    In the scan-path tests:
    The test length was 16384 bits.
    The JTAG IR length was 6 bits.
    The JTAG DR length was 1 bits.

    The IR/DR scan-path tests used 4 frequencies.
    The IR/DR scan-path tests used 500.0kHz as the initial frequency.
    The IR/DR scan-path tests used 570.3kHz as the highest frequency.
    The IR/DR scan-path tests used 500.0kHz as the final frequency.

    -----[Measure the source and frequency of the final JTAG TCLKR input]--------

    The frequency of the JTAG TCLKR input is measured as 499.1kHz.

    The frequency of the JTAG TCLKR input and TCLKO output signals are similar.
    The target system likely uses the TCLKO output from the emulator PLL.

    -----[Perform the standard path-length test on the JTAG IR and DR]-----------

    This path-length test uses blocks of 512 32-bit words.

    The test for the JTAG IR instruction path-length succeeded.
    The JTAG IR instruction path-length is 6 bits.

    The test for the JTAG DR bypass path-length succeeded.
    The JTAG DR bypass path-length is 1 bits.

    -----[Perform the Integrity scan-test on the JTAG IR]------------------------

    This test will use blocks of 512 32-bit words.
    This test will be applied just once.

    Do a test using 0xFFFFFFFF.
    Scan tests: 1, skipped: 0, failed: 0
    Do a test using 0x00000000.
    Scan tests: 2, skipped: 0, failed: 0
    Do a test using 0xFE03E0E2.
    Scan tests: 3, skipped: 0, failed: 0
    Do a test using 0x01FC1F1D.
    Scan tests: 4, skipped: 0, failed: 0
    Do a test using 0x5533CCAA.
    Scan tests: 5, skipped: 0, failed: 0
    Do a test using 0xAACC3355.
    Scan tests: 6, skipped: 0, failed: 0
    All of the values were scanned correctly.

    The JTAG IR Integrity scan-test has succeeded.

    -----[Perform the Integrity scan-test on the JTAG DR]------------------------

    This test will use blocks of 512 32-bit words.
    This test will be applied just once.

    Do a test using 0xFFFFFFFF.
    Scan tests: 1, skipped: 0, failed: 0
    Do a test using 0x00000000.
    Scan tests: 2, skipped: 0, failed: 0
    Do a test using 0xFE03E0E2.
    Scan tests: 3, skipped: 0, failed: 0
    Do a test using 0x01FC1F1D.
    Scan tests: 4, skipped: 0, failed: 0
    Do a test using 0x5533CCAA.
    Scan tests: 5, skipped: 0, failed: 0
    Do a test using 0xAACC3355.
    Scan tests: 6, skipped: 0, failed: 0
    All of the values were scanned correctly.

    The JTAG DR Integrity scan-test has succeeded.

    TMS/TDO Output Timing)

    line
    4 512 - 01 00 500.0kHz {O} good value apply explicit tclk
    and
    The IR/DR scan-path tests used 500.0kHz as the final frequency.
    as I expected - final frequency low
    It's all what I did. I can't rise final frequency - max is 890.6kHz - as default

    Best regards
    Oleg

  • Hi Shankari,
    I tried use the video from processors.wiki.ti.com/.../Adaptive_Clocking
    as pattern for Adaptive Clocking. I have next results
    My first result - all fields Default (Fields JTAG TCLKFrequency (MHz) and
    TMS/TDO Output Timing)

    The result of a slightly different on pattern - I have the other emulator(Blackhawck XDS560v2 USB Mezzanine Emulator, and
    other version CCSv5.2, but I was confused next
    16 512 - 01 32 890.6kHz {O} good value auto margin initial
    The IR/DR scan-path tests used 890.6kHz as the final frequency.

    As I understand my really frequency clocking is 890.6kHz? Is it true?
    I did next experiment as to video, but my emulator to worked only
    Fields
    JTAG TCLKFrequency (MHz) - Fixed with user specified faster value
    --Enter a value from 0.5MHz to 64MHz 0.5MHz
    TMS/TDS Output Timing Failed edge is JTAG standart
    (any value send to error) - result bellow
    . . /
    Test Size Coord MHz Flag Result Description
    ~~~~ ~~~~ ~~~~~~~ ~~~~~~~~ ~~~~ ~~~~~~~~~~~ ~~~~~~~~~~~~~~~~~~~
    1 none - 01 00 500.0kHz - similar isit internal clock
    2 none - 01 09 570.3kHz {-} similar isit internal clock
    3 512 - 01 00 500.0kHz O good value measure path length
    4 512 - 01 00 500.0kHz {O} good value apply explicit tclk
    The IR/DR scan-path tests used 4 frequencies.
    The IR/DR scan-path tests used 500.0kHz as the initial frequency.
    The IR/DR scan-path tests used 570.3kHz as the highest frequency.
    The IR/DR scan-path tests used 500.0kHz as the final frequency.
    as I expected - final frequency low
    It's all what I did. I can't rise final frequency - max is 890.6kHz - as default

    Best regards
    Oleg
  • Hi Shankari,
    I tried use the video from processors.wiki.ti.com/.../Adaptive_Clocking
    as pattern for Adaptive Clocking. I have next results
    My first result - all fields Default (Fields JTAG TCLKFrequency (MHz) and
    TMS/TDO Output Timing)

    The result of a slightly different on pattern - I have the other emulator(Blackhawck XDS560v2 USB Mezzanine Emulator, and
    other version CCSv5.2, but I was confused next
    16 512 - 01 32 890.6kHz {O} good value auto margin initial
    The IR/DR scan-path tests used 890.6kHz as the final frequency.

    As I understand my really frequency clocking is 890.6kHz? Is it true?
    I did next experiment as to video, but my emulator to worked only
    Fields
    JTAG TCLKFrequency (MHz) - Fixed with user specified faster value
    --Enter a value from 0.5MHz to 64MHz 0.5MHz
    TMS/TDS Output Timing Failed edge is JTAG standart
    (any value send to error) - result bellow
    . . /
    Test Size Coord MHz Flag Result Description
    ~~~~ ~~~~ ~~~~~~~ ~~~~~~~~ ~~~~ ~~~~~~~~~~~ ~~~~~~~~~~~~~~~~~~~
    1 none - 01 00 500.0kHz - similar isit internal clock
    2 none - 01 09 570.3kHz {-} similar isit internal clock
    3 512 - 01 00 500.0kHz O good value measure path length
    4 512 - 01 00 500.0kHz {O} good value apply explicit tclk
    The IR/DR scan-path tests used 4 frequencies.
    The IR/DR scan-path tests used 500.0kHz as the initial frequency.
    The IR/DR scan-path tests used 570.3kHz as the highest frequency.
    The IR/DR scan-path tests used 500.0kHz as the final frequency.
    as I expected - final frequency low
    It's all what I did. I can't rise final frequency - max is 890.6kHz - as default

    Best regards
    Oleg
  • Hi Andy,
    I am apologize for my incorrect answer.
    I followed by your advice and I did precompiled library. I did change BUFSIZ from 256 to 512. I did changes of file format - from char to bin. I tried to experiment with fread function. As the result - my best result gave less time is about six time.
    I think this due JTAG. I decide to stop work with files as data source. Maybe I am wrong.
    Best regards,
    Oleg