C6678: H.264 Encoder hanging when 3+ cores are invovled

Hi Chris,

In 3 cores scenario, Is create call returned success.

Is it working fine with cache disabled?

Do you have source code access to H264HP Encoder?

Thanks and regards

Sudheesh

Sudheesh,

I forgot to mention in my initial post, but I am using Advantech's 8681 PCIe card for my tests. 

As far as I can tell, the create call is successful. After the call, I am checking if the returned handle is NULL. Is this sufficient to determine if the call failed?

I've tested various configurations of L1 and L2 cache sizes including both set to size 0, but so far it hasn't made any difference.

I do have source code access to H264HP Encoder and currently have the source for the same version that I've been testing with (01.00.01.04).

I am attaching the debug trace binary that I have. Let me know if there is any useful info in it or how I can obtain the debug trace parser utility to view this info myself.

trace.tar.gz

Regards,
Chris

Hi Chris, have you tried latest H264HP encoder? some bugs have been fixed..

http://software-dl.ti.com/dsps/dsps_public_sw/codecs/C6678/H264HP_E/latest/index_FDS.html

Paula,

I tried using the lib file in the latest encoder version, but with this lib file the create call is failing for me even when only using 1 core. I will need to look into this more to figure out which configuration params are causing this problem. I was surprised to see that my static param settings were okay with an older lib version but not with the latest. 

Regards,
Chris

Chris, apologize my delay reply.. didn't see your reply before..

For using H264HP encoder 1.0.3.0 Please try to increase CODEC_SCRATCH_SIZE from 0x00D00000 to 0x00D80000. Also attached new codec params configuration file example. This new release includes a new param "suppressHighFreqCoeffs"1031.codecParams.cfg

thank you,

Paula

Paula,

Adding the suppressHighFreqCoeffs parameter seems to have fixed the issue I was seeing with the create call. I couldn't find CODEC_SCRATCH_SIZE though.

With the updated lib version, I still see the issue when using 3 cores.

Is there anything in the debug trace to indicate what might've went wrong? How can I get the debug trace into a readable format?

Chris

Chris,

Hope you have updated interface files(h264hpvenc_ti.h, ih264hpvenc.h, ividmc.h) also when you migrated to latest version.

If you have hang issue when 3 cores are used, debug mode lib(since you have source code access) and ccs will be better tool to debug than debug trace, if you have JTAG enabled in board. You can pause at the hang point to see what went wrong. 

As you have already tried disabling cache and your 2-core outputs are fine, further we need to look at point at which hang happens like during EDMA call/Barrier/Memory error.

Thanks and regards

Sudheesh 

Hello,

When three cores are used for H264 Encoding, all the cores are getting stuck at the call

ECPY_directWait(dmaHandle)    

ECPY_directWait(dmaHandle) is getting called from VIDEO_TI_DMA_wait function (in video_ti_ecpy.h) and  VIDEO_TI_DMA_wait function is called from H264HPVENC_TI_scaledwn_4h4v_pad function (in h264hpvenc_ti_scaledwn_4h4v.c). 

H264HPVENC_TI_scaledwn_4h4v_pad function is getting called from H264HPVENC_TI_encode_int function (in h264hpvenc_ti_frameprocess.c) 

We looked at some links and, they might be related, but not sure. 

http://e2e.ti.com/support/embedded/multimedia_software_codecs/f/356/p/338844/1201600
https://e2e.ti.com/support/embedded/multimedia_software_codecs/f/356/p/229062/875828 
http://e2e.ti.com/support/embedded/multimedia_software_codecs/f/356/p/229062/875171#875171

Once cores get stuck, I have to reboot the server and card to run any H264 tests, but I can run other c66x applications. 

What can we do to debug this further?

Thanks
Anish 

Hi Sudheesh,

H.264 Encoder when used with 3 cores is not getting stuck when dma transfer is disabled ( I defined CPU_COPY_ENABLED in the h264hpvenc_ti_c66x library to disable DMA), but output was corrupted.

When 3 cores are used, channel 18 is used by core 3. Is channel 18 supposed to be used or not?

Also why is edma instance hard coded to 1?   When shd we use instance #0, #1, or #2 and how to know which instance to use?
 
EDMA3_PARAMS.regionConfig = &C6678_Instance_config[1][DNUM];

const EDMA3_InstanceInitConfig C6678_Instance_config[3][8] =
{
/* EDMA3 INSTANCE# 0 */
{ regionSample0, regionSample0, regionSample0, regionSample0,
regionSample0, regionSample0, regionSample0, regionSample0
},
/* EDMA3 INSTANCE# 1 */
{ regionSample1, regionSample2, regionSample3, regionSample4,
regionSample5, regionSample6, regionSample7, regionSample8
},
/* EDMA3 INSTANCE# 2 */
{ regionSample1, regionSample2, regionSample3, regionSample4,
regionSample5, regionSample6, regionSample7, regionSample8
}
};

Thanks
Anish

Sudheesh-

As noted in our original post, we are using the 8681 and 8682 PCIe cards, and with those cards we use DMA channels as defined in the TI SDK PCIe driver.

What is the recommended DMA channel allocation for H.264 when combined with PCIe cards ?  Even if we get 3 cores to work, then I'm worried about 4-8.  It seems like this should be a basic scenario and well documented, maybe somehow we have missed a key piece of documentation.

Thanks.

-Jeff
Signalogic

Hello,

While testing H.264 Encoder with 3 cores, Core 0 always seem to be using DMA channel 0, Core 1 always seem to be using channel 8.
Core 2 sometimes uses channel 16, sometimes channel 18, other times channel 20.

Why  DMA channel number used by Core 2 keeps varying and how is that decision made on which DMA channel Core 2 uses? 

Also how can I check whether channel is in active state before calling ECPY_directConfigure function?

Thanks

-Anish

Hi Palachandra,

Thanks for the detailed reply. We are able to run encoder on 3+ cores by not having the timer/clock configuration in the cfg file and by increasing the BIOS heap size.

Thanks
Anish 

Hi Anish,

Thank you for the update, can you please mark the thread as answered.

Thanks and Regards,
Palachandra M V
www.pathpartnertech.com