Hello,
One of my customer was designing C6678 target board with 64bit DDR3 (16bit DDR x4) by following design guides related to DDR3:
- Hardware Design Guide for KeyStone I Devices
- DDR3 Design Requirements for KeyStone Devices
But now they are considering to change 32bit DDR3 (16bit DDR x2) with minimal hardware change (almost same layout, connection, etc. just considering to disable upper side of DDR[32-63] and its control lines).
I believe DDR3 32bit would not work with the HW design for 64bit configuration, but they would like to have your comment on this. Any suggestion ?
Also, I have a question. If ECC feature is not required, I think DDRCB[7:0] should be floating. Correct, right ?
Best Regards,
Naoki Kawada