Hello everyone
I am implementing Double Buffer (or Ping-Pong Buffer) mechanism to make the calculation (thousands of vector dot production) more efficient. So I create four buffers, InBuff_A, InBuff_B, OutBuff_A, and OutBuff_B. Each of them are 192KB, and place on MSMC, which configured as Shared Level 2 memory. L1D is configured as FULL cache. As we know, the data on MSMC is not cacheable at L2. (I did not use XMC changing MSMC address). So the data in the MSMC are only cached in L1D.
The dot production is performed in this way: a MidBuff is created on L2 SRAM. MidBuff would store the multiplication results of two vectors (One vector is from InBuff, another one is a fix vector stored on L2 SRAM). After adding each value in MidBuff, the final value is stored in a vector, named FINAL, on L2 SRAM. At last, I would use some lines, like OutBuff = FINAL, making the result back to MSMC.
Q1: From my understanding, as FINAL is on the L2 SRAM, which has Snoop Coherence Protocol with L1D, so when I do OutBuff = FINAL, a Snoop-Read would be performed. This would make the OutBuff data on MSMC is "up-to-date". Is that correct?
Q2: As the size of each Buffer is larger than 32KB, L1D cannot be fully cached the data from InBuff_A or InBuff_B (Capacity Miss). From the knowledge I learned from C66x DSP Cache User Guide, there is no need to maintain the cache coherency between the InBuff and L1D, because L1D would evict the old data when read miss happened.
Q3: How can I know how much of data is cached in L1D from InBuff?
Q4: A specific 192 Bytes long vector is multiplied by other same length vectors for 1024 times. When read misses happened, will this re-used vector be evicted?
Thanks.
Xining
