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66AK2H06 IBIS model error

le pham
Prodigy 50 points
Other Parts Discussed in Thread: 66AK2H06

When I tried to import IBIS model for 66ak2h06 (66ak2h06_12_r1p4.ibs), that I downloaded from TI website, into HyperLynx tool, I got these errors:

------------------------------------------------------------------------------------------------------------------------------------------------------------------

C:/66ak2h06_12_r1p4.ibs(213344) : Error : Pin model s_iclkrx0p9gv used by the series pin mapping from pin AW35 to pin AW34 of component 66ak2hxx does not exist in this file.
C:/66ak2h06_12_r1p4.ibs(213344) : Error : Pin model s_iclkrx0p9gv used by the series pin mapping from pin AW32 to pin AW31 of component 66ak2hxx does not exist in this file.
C:/66ak2h06_12_r1p4.ibs(213344) : Error : Pin model s_iclkrx0p9gv used by the series pin mapping from pin AV34 to pin AV33 of component 66ak2hxx does not exist in this file.
C:/66ak2h06_12_r1p4.ibs(213344) : Error : Pin model s_iclkrx0p9gv used by the series pin mapping from pin AR39 to pin AR38 of component 66ak2hxx does not exist in this file.
C:/66ak2h06_12_r1p4.ibs(213344) : Error : Pin model s_iclkrx0p9gv used by the series pin mapping from pin A25 to pin B25 of component 66ak2hxx does not exist in this file.
C:/66ak2h06_12_r1p4.ibs(213344) : Error : Pin model s_iclkrx0p9gh used by the series pin mapping from pin AK3 to pin AL3 of component 66ak2hxx does not exist in this file.
C:/66ak2h06_12_r1p4.ibs(213344) : Error : Pin model s_iclkrx0p9gh used by the series pin mapping from pin B37 to pin C37 of component 66ak2hxx does not exist in this file.
C:/66ak2h06_12_r1p4.ibs(213344) : Error : Pin model s_iclkrx0p9gh used by the series pin mapping from pin AL2 to pin AM2 of component 66ak2hxx does not exist in this file.
Error : Parse failed on file C:/66ak2h06_12_r1p4.ibs.
C:\66ak2h06_12_r1p4.ibs - 9 error(s), 21 warnings(s)

------------------------------------------------------------------------------------------------------------------------------------------------------------------

Can somebody show me how to resolve this problem. Thank you in advance.

  • 0
    TI__Mastermind 43660 points
    Hello Le,

    A similar issue is already addressed in below thread. Please have a look and let me know if you have further clarification.

    e2e.ti.com/.../416721

    Regards,
    Senthil
  • 0
    TI__Guru* 81335 points

    Welcome to the TI E2E forum. I hope you will find many good answers here and in the TI.com documents and in the TI Wiki Pages (for processor issues). Be sure to search those for helpful information and to browse for the questions others may have asked on similar topics (e2e.ti.com). Please read all the links below my signature.

  • 0 in reply to Senthilkumar Srinivasan
    Prodigy 50 points

    Hi Senthil,

    Thank you for your response. Could you please suggest a IBIS Model for 66AK2H06 that can be used with HyperLynx?

    Regards,
    Le.

  • 0 in reply to le pham
    TI__Mastermind 43660 points
    Hello Le,

    Could you please try the workaround (replacing the statements) given by Bill Taboada in below thread and let me know if it works for you ?

    e2e.ti.com/.../1482046

    Regards,
    Senthil
  • 0 in reply to Senthilkumar Srinivasan
    Prodigy 50 points
    Hi Senthil,

    I edited the IBIS model as suggested and now I can assign it to the device.

    Thank you for your help.
  • 0 in reply to le pham
    TI__Mastermind 43660 points
    Hello Le,

    Thanks for the update.

    Regards,
    Senthil
  • 0 in reply to Senthilkumar Srinivasan
    Prodigy 50 points
    Hi Senthil,

    Now I am facing another problem. When I run DDR3 simulation, we got this error:
    -----------------------------------------------------------------------------------------------------------------------
    The following controller nets have inconsistent differential pins attached, based on IBIS modeling:

    Clock Net: SOC_DDR3A_ECKN_0 ---
    Pin: U3.K7 (-) IBIS Signal: v80a.ibs [MT41J256M16HA] CK#
    Pin: U4.K7 (-) IBIS Signal: v80a.ibs [MT41J256M16HA] CK#
    Pin: U5.K7 (-) IBIS Signal: v80a.ibs [MT41J256M16HA] CK#
    Pin: U6.K7 (-) IBIS Signal: v80a.ibs [MT41J256M16HA] CK#
    Pin: U24.B12 (not differential) IBIS Signal: 66ak2h06_12_r1p4_edited.ibs [66ak2hxx] DDR3ACLKOUTN0

    Clock Net: SOC_DDR3A_ECKP_0 ---
    Pin: U3.J7 (+) IBIS Signal: v80a.ibs [MT41J256M16HA] CK
    Pin: U4.J7 (+) IBIS Signal: v80a.ibs [MT41J256M16HA] CK
    Pin: U5.J7 (+) IBIS Signal: v80a.ibs [MT41J256M16HA] CK
    Pin: U6.J7 (+) IBIS Signal: v80a.ibs [MT41J256M16HA] CK
    Pin: U24.A12 (not differential) IBIS Signal: 66ak2h06_12_r1p4_edited.ibs [66ak2hxx] DDR3ACLKOUTP0

    Clock Net: SOC_DDR3B_ECKN_0 ---
    Pin: U24.AD39 (not differential) IBIS Signal: 66ak2h06_12_r1p4_edited.ibs [66ak2hxx] DDR3BCLKOUTN0
    Pin: U39.K7 (-) IBIS Signal: v80a.ibs [MT41J256M16HA] CK#
    Pin: U40.K7 (-) IBIS Signal: v80a.ibs [MT41J256M16HA] CK#
    Pin: U42.K7 (-) IBIS Signal: v80a.ibs [MT41J256M16HA] CK#
    Pin: U43.K7 (-) IBIS Signal: v80a.ibs [MT41J256M16HA] CK#

    Clock Net: SOC_DDR3B_ECKP_0 ---
    Pin: U24.AD38 (not differential) IBIS Signal: 66ak2h06_12_r1p4_edited.ibs [66ak2hxx] DDR3BCLKOUTP0
    Pin: U39.J7 (+) IBIS Signal: v80a.ibs [MT41J256M16HA] CK
    Pin: U40.J7 (+) IBIS Signal: v80a.ibs [MT41J256M16HA] CK
    Pin: U42.J7 (+) IBIS Signal: v80a.ibs [MT41J256M16HA] CK
    Pin: U43.J7 (+) IBIS Signal: v80a.ibs [MT41J256M16HA] CK
    -----------------------------------------------------------------------------------------------------------------------
    It seems like the clock pins weren't configured as differential in 66ak2h06 IBIS model. Could you please check and advise?

    Regards,
    Le.
  • 0 in reply to le pham
    TI__Mastermind 42545 points

    Hi Le,

    The clocks have not been declared differential in the [Diff_pin] statement. Try adding the following lines to that section.

    AD38 AD39 200mV NA NA NA || DDR3BCLKOUTP0 & DDR3BCLKOUTN0
    AC39 AC38 200mV NA NA NA || DDR3BCLKOUTP1 & DDR3BCLKOUTN1
    A12 B12 200mV NA NA NA || DDR3ACLKOUTP0 & DDR3ACLKOUTN0
    A13 B13 200mV NA NA NA || DDR3ACLKOUTP1 & DDR3ACLKOUTN1

    Regards,

    Bill

  • 0 in reply to Bill Taboada
    Prodigy 50 points

    Hi Bill,

    We edited the differential and it fixed that error. But after that, we got another message from HyperLynx

    --------------------------------------------------------------------------------

    These IBIS models have missing receiver voltage thresholds, which may affect analysis:
    IBIS File: C:\....\66ak2h06_12_r1p4_edited_150914.ibs
    IBIS Model: PDDRIO_D3FP3_48
    Model does not have a [Receiver Thresholds] section.
    Only Vinh and Vinl thresholds are specified in the [Model Spec] section, and will be used for both AC and DC thresholds.
    Net: SOC_DDR3A_EDQ0
    Controller pin: U24.G1 (DDR3AD00)
    Net: SOC_DDR3A_EDQ1
    Controller pin: U24.H2 (DDR3AD01)
    Net: SOC_DDR3A_EDQ2
    .....
    (and so on)

    IBIS Model: PDDRIO_D3FP3_ODT40
    Model does not have a [Receiver Thresholds] section.
    Missing Vinh and Vinl thresholds in the [Model Spec] section.
    Only Vinh and Vinl thresholds are specified in the [Model] section, and will be used for both AC and DC thresholds.
    Net: SOC_DDR3A_EDQ0
    Controller pin: U24.G1 (DDR3AD00)
    Net: SOC_DDR3A_EDQ1
    Controller pin: U24.H2 (DDR3AD01)
    Net: SOC_DDR3A_EDQ2
    Controller pin: U24.F1 (DDR3AD02)
    Net: SOC_DDR3A_EDQ3
    Controller pin: U24.G2 (DDR3AD03)
    ......
    (and so on)


    These nets have inappropriate IBIS model types attached, for the selected simulations:
    Net: SOC_DDR3A_EDM_0 (Data Mask Net)
    Controller pin: U24.C2 (DDR3ADQM0) --Model is input only, but needs to be output or I/O
    ODT Enabled Model (write): C:\MentorGraphics\9.2HL\SDD_HOME\hyperlynx64\LIBS\66ak2h06_12_r1p4_edited_150914.ibs[66ak2hxx] PDDRIO_D3FP3_ODT40

    Net: SOC_DDR3A_EDM_1 (Data Mask Net)
    Controller pin: U24.F3 (DDR3ADQM1) --Model is input only, but needs to be output or I/O
    ODT Enabled Model (write): C:\MentorGraphics\9.2HL\SDD_HOME\hyperlynx64\LIBS\66ak2h06_12_r1p4_edited_150914.ibs[66ak2hxx] PDDRIO_D3FP3_ODT40
    .....
    (and so on)

    ---------------------------------------------------------------------------

    Could you please take a look and advise?

    Regards,

    Le.

    P.S Here is the log file

    DDRWizLog.rtf

  • 0 in reply to le pham
    TI__Mastermind 42545 points
    Hi Le,
    [Receiver threshold] is listed as optional in the IBIS spec and was not delivered with the models we received for the DDR3 IOs. We have requested that the thresholds be added but it's unlikely that will happen any time soon. Sorry for the inconvenience.
    Regards,
    Bill