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DDR3 unused addresses

Thibaut B
Prodigy 80 points

Hello,

I have a question concerning the wiring of the unused addresses of DDR3 packages to a Keystone II.

We plan to use 2 packages of 1Gb on 16bits (2x 8 Meg x 16 bits x 8 banks).
We worry about the obsolescence of this memory. If in the future, we must mount a 2Gb (or 4Gb) as the 1Gb is no longer produced, the address A[13] (and A[15]/A[14] for a 4Gb and 8Gb) of this memory will not be NC. As it does not seem to be any pulldown internally, parasites could move the MSB of the address and make our design ineffective. That’s why we think to put the balls A[15..13] that are currently NC to GND if in a few years these balls become the MSB addresses of higher size memory components.

If a component memory size change is imposed, we do not intend to change neither our hardware design nor the soft into the Keystone II. So we would like to make the Keystone II "believe" that it still runs with 1Gb memories.

Question : What should we do with address signals A[15..13]? Can we simply connect it to GND (it seems dangerous to leave it NC)? Or should it absolutely be connected to the Keystone II? (we want to avoid this to simplify our layout).
 
Thank you in advance for your reply.

  • 0
    TI__Guru* 81335 points

    Welcome to the TI E2E forum. I hope you will find many good answers here and in the TI.com documents and in the TI Wiki Pages (for processor issues). Be sure to search those for helpful information and to browse for the questions others may have asked on similar topics (e2e.ti.com). Please read all the links below my signature.

    We will get back to you on the above query shortly. Thank you for your patience.

  • 0
    TI__Guru* 81335 points

    We have of design guides and schematic checklists for keystone devices. Please get back to us if these documents does not answer your question,

    K2H: 

    K2E: 

    Schematic Checklist:

    Please adhere to the design requirements described in above documents. Thank you.

  • 0
    TI__Mastermind 43660 points
    Hello Thibaut,

    If you designing the board to support 1Gb, 2Gb, 4Gb and 8Gb memory devices, you are required to route the address lines A[15..13] right from the Keystone II device to the memories.

    The lower capacity memories would have MSB address pins reserved and there won't be any issues in connecting MSB lines to reserved pins.

    Regards,
    Senthil
  • 0 in reply to Senthilkumar Srinivasan
    Prodigy 80 points
    Hello Senthil,

    Thanks for your reply.

    In fact I don't need to design the board to support memories higher than 1Gb, that's why I don't want to route the address lines A[15..13] (my layout is very complex). But in case if in ten years only the 2Gb memory is still available (for exemple the manufacturing of the 1Gb is stopped), I want to be sure that my design will still run with memories higher than 1Gb (with of course only 1Gb addressable).
    That's why I planned to put the address lines A[15..13] to GND (they are NC on the 1Gb package but can become real addresses on higher capacity memories).

    But I don't know if it is ok for the memory to have the A[15..13] fixed to GND (and if the Keystone II will not need these addresses to initiate its memory controler).

    Regards,
    Thibaut
  • 0 in reply to Thibaut B
    TI__Mastermind 43660 points
    Hello Thibaut,

    Usually the unused address pins will be left unconnected and there would not be an issue leaving like this. If you ground these pins for 1Gb memory and then you move on to higher memories, you may not be able to access higher memory areas corresponds to A[15..13].

    So i would advice you to route the signals from controller to memory to support all range of memories.

    Regards,
    Senthil
  • 0 in reply to Senthilkumar Srinivasan
    Prodigy 80 points
    Yes but I don't want to access higher memory areas corresponds to A[15..13], I just need to not change neither the hardware design nor the soft into the Keystone II if a bigger memory is mounted insted of a 1Gb.

    So I just need to know if it is correct to connect A[15..13] to GND (and leave A[15..13] on the Keystone II side NC). I need to be sure that I must connect them to GND in order to avoid parasits on these addresses on a 2, 4 or 8Gb memory.

    Regards,
    Thibaut
  • 0 in reply to Thibaut B
    TI__Mastermind 43660 points
    Hello Thibaut,

    On Keystone 2 side, you can leave the pins NC. But on memory side i cannot comment on the pin connection. I think connecting the address pins to ground is fine. However i would like you to confirm this from the memory manufacturer.

    Regards,
    Senthil
  • 0 in reply to Senthilkumar Srinivasan
    Prodigy 80 points
    Ok thank you, I already contact him and I am waiting for his answer.

    Regards,
    Thibaut
  • 0 in reply to Thibaut B
    Prodigy 80 points
    I received the answer from Micron, they recommand to pulldown them (if possible, otherwise to GND is also fine).

    Regards,
    Thibaut
  • 0 in reply to Thibaut B
    TI__Mastermind 43660 points
    Thanks for your update.

    Regards,
    Senthil