I have my CCS project wherein all the sections such as .text, .stack etc are place in the L2SRAM.
But this gives a linker error as this much memory is not available in L2SRAM
So In experiment 1), I placed all of them in the MSMCSRAM
in experiment 2) I tried changing the L2SRAM to the MSMCSRAM pool and commented MSMCSRAM section
MEMORY
{
L1PSRAM (RWX): org = 0x00e00000, len = 0x8000
L1DSRAM (RWX): org = 0x00f00000, len = 0x8000
L2SRAM (RWX) : org = 0x800000, len = 0x80000
DDR3 (RWX): org = 0x80000000, len = 0x20000000
MSMCSRAM (RWX) : org = 0xc000000, len = 0x400000
}
SECTIONS
{
.text: load >> MSMCSRAM
.ti.decompress: load > MSMCSRAM
.stack: load > MSMCSRAM
GROUP: load > MSMCSRAM
{
.bss:
.neardata:
.rodata:
}
.cinit: load > MSMCSRAM
.pinit: load >> MSMCSRAM
.init_array: load > MSMCSRAM
.const: load >> MSMCSRAM
.data: load >> MSMCSRAM
.fardata: load >> MSMCSRAM
.switch: load >> MSMCSRAM
.sysmem: load > MSMCSRAM
.far: load >> MSMCSRAM
.args: load > MSMCSRAM align = 0x4, fill = 0 {_argsize = 0x0; }
.cio: load >> MSMCSRAM
.ti.handler_table: load > MSMCSRAM
.c6xabi.exidx: load > MSMCSRAM
.c6xabi.extab: load >> MSMCSRAM
.vecs: load > MSMCSRAM
xdc.meta: load > MSMCSRAM, type = COPY
}
But some point the system runs into an exception
[C66xx_0]
[C66xx_0] 0x0
B24=0x1904 B25=0x2021
B26=0xbad2fe37 B27=0xfdeffbb6
B28=0xc08bf78 B29=0xffffffff
B30=0xffffffff B31=0x0
NTSR=0x1020d
ITSR=0x400d
IRP=0xc0264a8
SSR=0x0
AMR=0x0
RILC=0x0
ILC=0x0
Exception at 0xc0[C66xx_0] ac8cc
EFR=0x2 NRP=0xc0ac8cc
Internal exception: IERR=0x8
Opcode exception
ti.sysbios.family.c64p.Exception: line 248: E_exceptionMin: pc = 0x0c0ac8cc, sp = 0x0c0ac8a0.
To see more exception detail, use ROV or set 'ti.sysbios.family.c64p.Exception.enablePri[C66xx_0] nt = true;'
xdc.runtime.Error.raise: terminating
So is this problem arising due to the above fancy configurations? The only problem for me is to get a very big L2SRAM memory pool...
Can somebody please help...?