DSP is TMS320C6678.There are two DSPs on my board and the JTAG is daisy-chain.
Connect the core 0 of DSP1, DSP1 is ok. Thenwhen I connect the core 0 of DSP2, the bug appears and the core 0 of DSP1 failed to connect.
C66xx_0: GEL Output:
Connecting Target...
C66xx_0: GEL Output: DSP core #0
C66xx_0: GEL Output: C6678L GEL file Ver is 2.004
C66xx_0: GEL Output: Global Default Setup...
C66xx_0: GEL Output: Setup Cache...
C66xx_0: GEL Output: L1P = 32K
C66xx_0: GEL Output: L1D = 32K
C66xx_0: GEL Output: L2 = ALL SRAM
C66xx_0: GEL Output: Setup Cache... Done.
C66xx_0: GEL Output: Main PLL (PLL1) Setup ...
C66xx_0: GEL Output: PLL in Bypass ...
C66xx_0: GEL Output: PLL1 Setup for DSP @ 1000.0 MHz.
C66xx_0: GEL Output: SYSCLK2 = 333.3333 MHz, SYSCLK5 = 200.0 MHz.
C66xx_0: GEL Output: SYSCLK8 = 15.625 MHz.
C66xx_0: GEL Output: PLL1 Setup... Done.
C66xx_0: GEL Output: Power on all PSC modules and DSP domains...
C66xx_0: GEL Output: Security Accelerator disabled!
C66xx_0: GEL Output: Power on all PSC modules and DSP domains... Done.
C66xx_0: GEL Output: PA PLL (PLL3) Setup ...
C66xx_0: GEL Output: PA PLL Setup... Done.
C66xx_0: GEL Output: DDR3 PLL (PLL2) Setup ...
C66xx_0: GEL Output: DDR3 PLL Setup... Done.
C66xx_0: GEL Output: DDR begin (1333 auto)
C66xx_0: GEL Output: XMC Setup ... Done
C66xx_0: GEL Output:
DDR3 initialization is complete.
C66xx_0: GEL Output: DDR done
C66xx_0: GEL Output: DDR3 memory test... Started
C66xx_0: GEL Output: DDR3 memory test... Passed
C66xx_0: GEL Output: PLL and DDR Initialization completed(0) ...
C66xx_0: GEL Output: configSGMIISerdes Setup... Begin
C66xx_0: GEL Output:
SGMII SERDES has been configured.
C66xx_0: GEL Output: Enabling EDC ...
C66xx_0: GEL Output: L1P error detection logic is enabled.
C66xx_0: GEL Output: L2 error detection/correction logic is enabled.
C66xx_0: GEL Output: MSMC error detection/correction logic is enabled.
C66xx_0: GEL Output: Enabling EDC ...Done
C66xx_0: GEL Output: Configuring CPSW ...
C66xx_0: GEL Output: Configuring CPSW ...Done
C66xx_0: GEL Output: Global Default Setup... Done.
Connecting Target...
C66xx_8: GEL Output: DSP core #0
C66xx_8: GEL Output: C6678L GEL file Ver is 2.004
C66xx_8: GEL Output: Global Default Setup...
C66xx_8: GEL Output: Setup Cache...
C66xx_8: GEL Output: L1P = 32K
C66xx_8: GEL Output: L1D = 32K
C66xx_8: GEL Output: L2 = ALL SRAM
C66xx_8: GEL Output: Setup Cache... Done.
C66xx_8: GEL Output: Main PLL (PLL1) Setup ...
C66xx_8: GEL Output: PLL in Bypass ...
C66xx_8: GEL Output: PLL1 Setup for DSP @ 1000.0 MHz.
C66xx_8: GEL Output: SYSCLK2 = 333.3333 MHz, SYSCLK5 = 200.0 MHz.
C66xx_8: GEL Output: SYSCLK8 = 15.625 MHz.
C66xx_8: GEL Output: PLL1 Setup... Done.
C66xx_8: GEL Output: Power on all PSC modules and DSP domains...
C66xx_8: Trouble Reading Memory Block at 0x2350810 on Page 0 of Length 0x4: (Error -1139 @ 0x2350810) Lost debug connection to device. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 5.0.872.0)
C66xx_8: GEL: Error while executing OnTargetConnect(): target access failed at (*(mdstat)&0x1f) [V6_6678.gel:1288] at Set_PSC_State(0, 4, 0x3) [V6_6678.gel:1740] at Set_Psc_All_On() [V6_6678.gel:867] at Global_Default_Setup_Silent() [V6_6678.gel:577] at OnTargetConnect() .
C66xx_0: Power Failure on Target CPU
