C6678 EMAC boot fails when *.eth is bigger than ~1MB

/*
 * Do not modify this file; it is automatically generated from the template
 * linkcmd.xdt in the ti.targets.elf package and will be overwritten.
 */

/*
 * put '"'s around paths because, without this, the linker
 * considers '-' as minus operator, not a file name character.
 */


-l"C:\project\workspace_v5_4\Debug\configPkg\package\cfg\app_pe66.oe66"
-l"C:\project\workspace_v5_4\PTB_DSP\src\sysbios\sysbios.ae66"
-l"C:\ti\pdk_C6678_1_1_2_6\packages\ti\drv\qmss\lib\ti.drv.qmss.ae66"
-l"C:\ti\xdctools_3_25_00_48\packages\ti\targets\rts6000\lib\ti.targets.rts6000.ae66"
-l"C:\ti\xdctools_3_25_00_48\packages\ti\targets\rts6000\lib\boot.ae66"

--retain="*(xdc.meta)"


--args 0x0
-heap  0x0
-stack 0x2000

MEMORY
{
    MSMCSRAM (RWX) : org = 0xc000000, len = 0x200000
    L1DSRAM (RW) : org = 0xf00000, len = 0x8000
    L1PSRAM (RWX) : org = 0xe00000, len = 0x8000
    L2SRAM (RWX) : org = 0x800200, len = 0xffe00
    DDR3 (RWX) : org = 0x80000000, len = 0x40000000
    L2SRAM_BOARD_INFO (RWX) : org = 0x800100, len = 0x100
    L2SRAM_INT_VECT (RWX) : org = 0x800000, len = 0x100
    CORE0_L2SRAM (RWX) : org = 0x10800200, len = 0xffe00
    CORE0_L1PSRAM (RWX) : org = 0x10e00000, len = 0x8000
    CORE0_L1DSRAM (RWX) : org = 0x10f00000, len = 0x8000
    CORE0_L2SRAM_BOARD_INFO (RWX) : org = 0x10800100, len = 0x100
    CORE0_L2SRAM_INT_VECT (RWX) : org = 0x10800000, len = 0x100
}

/*
 * Linker command file contributions from all loaded packages:
 */

/* Content from xdc.services.global (null): */

/* Content from xdc (null): */

/* Content from xdc.corevers (null): */

/* Content from xdc.shelf (null): */

/* Content from xdc.services.spec (null): */

/* Content from xdc.services.intern.xsr (null): */

/* Content from xdc.services.intern.gen (null): */

/* Content from xdc.services.intern.cmd (null): */

/* Content from xdc.bld (null): */

/* Content from ti.targets (null): */

/* Content from ti.targets.elf (null): */

/* Content from xdc.rov (null): */

/* Content from xdc.runtime (null): */

/* Content from ti.targets.rts6000 (null): */

/* Content from ti.sysbios.interfaces (null): */

/* Content from ti.sysbios.family (null): */

/* Content from xdc.services.getset (null): */

/* Content from ti.sysbios.hal (null): */

/* Content from ti.drv.qmss (null): */

/* Content from ti.sysbios.family.c66 (ti/sysbios/family/c66/linkcmd.xdt): */

/* Content from ti.sysbios.rts (null): */

/* Content from xdc.runtime.knl (null): */

/* Content from ti.sysbios.family.c62 (null): */

/* Content from ti.sysbios.family.c64p.tci6488 (null): */

/* Content from ti.catalog.c6000 (null): */

/* Content from ti.catalog (null): */

/* Content from ti.catalog.peripherals.hdvicp2 (null): */

/* Content from xdc.platform (null): */

/* Content from xdc.cfg (null): */

/* Content from ti.platforms.generic (null): */

/* Content from amc4C6678_1250 (null): */

/* Content from ti.sysbios (null): */

/* Content from ti.sysbios.knl (null): */

/* Content from ti.sysbios.family.c64p (ti/sysbios/family/c64p/linkcmd.xdt): */

/* Content from ti.sysbios.family.c66.tci66xx (null): */

/* Content from ti.sysbios.gates (null): */

/* Content from ti.sysbios.xdcruntime (null): */

/* Content from ti.sysbios.timers.timer64 (null): */

/* Content from ti.sysbios.heaps (null): */

/* Content from ti.sysbios.utils (null): */

/* Content from configPkg (null): */

/* Content from xdc.services.io (null): */


/*
 * symbolic aliases for static instance objects
 */
xdc_runtime_Startup__EXECFXN__C = 1;
xdc_runtime_Startup__RESETFXN__C = 1;
TSK_idle = ti_sysbios_knl_Task_Object__table__V + 0;

SECTIONS
{
    .text: load >> L2SRAM
    .ti.decompress: load > L2SRAM
    .stack: load > L2SRAM
    GROUP: load > L2SRAM
    {
        .bss:
        .neardata:
        .rodata:
    }
    .cinit: load > L2SRAM
    .pinit: load >> L2SRAM
    .init_array: load > L2SRAM
    .const: load >> L2SRAM
    .data: load >> L2SRAM
    .fardata: load >> L2SRAM
    .switch: load >> L2SRAM
    .sysmem: load > L2SRAM
    .far: load >> L2SRAM
    .args: load > L2SRAM align = 0x4, fill = 0 {_argsize = 0x0; }
    .cio: load >> L2SRAM
    .ti.handler_table: load > L2SRAM
    .c6xabi.exidx: load > L2SRAM
    .c6xabi.extab: load >> L2SRAM
    .qmss: load > MSMCSRAM
    .vecs: load > L2SRAM
    xdc.meta: load > L2SRAM, type = COPY

}

void ethernet_rxIsr(UArg arg)
{
	emac_packet_poll(&my_netif);
}

static void ethernet_init_irq(void)
{
	Hwi_Params hwiParams;
	Error_Block eb;
	Uint32 eventId;

	Hwi_Params_init(&hwiParams);
	Error_init(&eb);

	/* Map the System Interrupt i.e. the Interrupt Destination 0 interrupt to the DIO ISR Handler. */
	CpIntc_dispatchPlug(CSL_INTC0_QM_INT_PASS_TXQ_PEND_12, (CpIntc_FuncPtr)ethernet_rxIsr, (UArg)0, TRUE);
	/* The configuration is for CPINTC0. We map system interrupt 112 to Host Interrupt 8. */
	CpIntc_mapSysIntToHostInt(0, CSL_INTC0_QM_INT_PASS_TXQ_PEND_12, 8);
	/* Enable the Host Interrupt. */
	CpIntc_enableHostInt(0, 8);
	/* Enable the System Interrupt */
	CpIntc_enableSysInt(0, CSL_INTC0_QM_INT_PASS_TXQ_PEND_12);
	/* Get the event id associated with the host interrupt. */
	eventId = CpIntc_getEventId(8);
	/* Host interrupt value*/
	hwiParams.arg = 8;
	/* Event id for your host interrupt */
	hwiParams.eventId = eventId;
	/* Enable the Hwi */
	hwiParams.enableInt = TRUE;
	/* This plugs the interrupt vector 4 and the ISR function. */
	/* When using CpIntc, you must plug the Hwi fxn with CpIntc_dispatch */
	/* so it knows how to process the CpIntc interrupts.*/
	Hwi_create(4, &CpIntc_dispatch, &hwiParams, &eb);

	if (Error_check(&eb)) {
		debug_print("Hwi_create() ERROR\n");
	}
}