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Cannot write to PCIE_SERDES_CFGPLL

Other Parts Discussed in Thread: TMS320C6678

In the IBL from C:\ti\mcsdk_2_01_02_06\tools\boot_loader\ibl, I modified the iblPCIeWorkaround() function to write a different value to the PCIE_SERDES_CFGPLL register. Instead of "DEVICE_REG32_W (PCIE_SERDES_CFG_PLL, 0x01C9);", I use "DEVICE_REG32_W (PCIE_SERDES_CFG_PLL, 0x01C9 | (2 << 11));".

After execution of the IBL, I run the CCS debugger to view the value at address 0x2620358. It returns a value of 0x000001c9. This is the default value according to sprugs6d.pdf section 2.3.1.1 "PCIe SerDes Configuration Register (PCIE_SERDES_CFGPLL)".

Why can I not change the value of the PCIE_SERDES_CFGPLL register? What do I need to do to change the value of this register?

I have also tried to comment out the following lines in devicePllConfig():

    *((Uint32 *)0x2620038) = 0x83e70b13;
    *((Uint32 *)0x262003c) = 0x95a4f1e0;

This had no effect, i.e. I continued to see 0x000001c9 when reading address 0x2620358 using the CCS debugger.

I am using a TMS320C6678, and the code I am modifying is in C:\ti\mcsdk_2_01_02_06\tools\boot_loader\ibl\src\device\c66x\c66xinit.c.

  • Hi Geoffrey,
    What is the boot mode selected? How the IBL has been loaded & executed/debugged? EVM or Custom board?

    Thank you.
  • Boot mode = I2C. IBL loaded onto EEPROM. Custom board. IBL executed by powering up board. When power up sequence completes, CCS debugger is used to read register.
  • Make sure to remove gel before connecting with core0. Thank you.
  • Hi,

    Have you set the I2C POST boot mode on your custom board? If yes, I2C POST boot is select the I2C EEPROM (at I2C address 0x50) and boot the flashed image. IBL is not execution on I2C POST boot mode. IBL is not required for no-boot, SPI, and I2C boot modes. For other boot modes only need IBL.

    Provide your boot mode selection details and share the serial port log at boot time.

    Thanks,
  • I reset the TMS320C6678, and made sure that it boots in "no boot" mode, then used CCS debugger to connect to the chip without a GEL file. From there, I used the CCS debugger memory browser to write the following:

    - 0x83e70b13 to address 0x2620038.

    - 0x95a4f1e0 to address 0x262003c.

    - 0x19c9 to address 0x2620358.

    After doing the above writes, CCS debugger memory browser shows a value of 0x1c9 at address 0x2620358. After the write to address 0x2620358, I noticed that the value at address 0x2620438 changes to 0x057abcaf.

  • Hi Geoffrey,
    Have you resolved the issue or not? It is confusing.

    Here is the procedure:
    1. Update the IBL in I2C using the EEPROM writer.
    2. Select the boot mode as I2C IBL.(Make sure custom board has two I2C like EVM or one(before programming i2c). The EVM uses this for POST(0x50) and IBL(0x51) respectively)
    3. Restart the board.
    4. Connect the core0 with debugger without gel file.
    5. Read the registers values and check.

    Note: Refer MCSDK 2.x User guide for programming I2C and writer.

    Thank you.
  • ???

    I am not having any problems loading the IBL to EEPROM.

    The problem is when I write to address 0x2620358, the value is not accepted even though I have correctly written to the kicker registers.
  • I have the same problem. My reference clock for PCIe is 250 MHz (not 100 MHz like on the EVM), so I need to write to PCIE_SERDES_CFGPLL 0x151, but the result is 50/50% - frequently (not always, but frequently) after correct write procedure (with kickers) I've read from PCIE_SERDES_CFGPLL 0x1C9 - the default value. Even after 20 tries - still 0x1C9 and as a result PLL doesn't lock.

    My code:

    n = 0;

        do
        {
        	CSL_BootCfgUnlockKicker();
    
        	CSL_BootCfgSetPCIEConfigPLL(0x151);
        	CSL_BootCfgGetPCIEConfigPLL(&cfg);
    
        	CSL_BootCfgLockKicker();
        }
        while ((cfg != 0x151) && ++n < 20);