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SOC power failure on K2H EVM

Hello everyone.

Sorry to bother your guys again.

We had purchased three K2H EVM (ver. A104-1) in this year from TI website. One of them, which purchased five months ago, was working at the beginning. Recently, this board does not work. The last working condition was the board powered up by external power cable came with K2H EVM, and nothing else connected with it. And then, it cannot be powered up without modifying BMC or any hardware. On the LCD of K2H EVM, it shows "SOC_PWR_STOPT". I followed the steps of updating BMC from this website,. The version of BMC I use is 1.0.2.6. However, after updating, the board does not work neither. The following is the output of BMC from the FTDI mini-USB on the EVM after the update. From the output, it shows an error :"Error: SOC_POWER_GOOD signal has de-asserted. Shutting down soc power."

In this thread, it mentions a similar problem as mine. So I check the C124 register. It is populated on our K2H EVM.

I had contacted with TI Technical Support by using email. They told us to open a new thread here and said that:" this team knows the K2HEVM better than anyone else and can advise with 100% certainty whether or not the failure that you're seeing is recoverable."

My question is: Can this problem be solved on my own? If it is not, can TI help me to fix that?

Thank You.

Xining

[00:00:00] BMC Init Begin
[00:00:00] BMC Version 1.0.2.6
[00:00:00] XTCIEVMK2X
[00:00:00] 4.0
[00:00:00] S/N: 108259
[00:00:00] BMC Init Complete
[00:00:00] Main PWR Start Begin
[00:00:00] Main PWR Start Complete
[00:00:00] SOC PWR Start Begin
[00:00:00] Testing register 0 of clock 1... Passed.
[00:00:00] Testing register 1 of clock 1... Passed.
[00:00:00] Testing register 2 of clock 1... Passed.
[00:00:00] Testing register 3 of clock 1... Passed.
[00:00:00] Testing register 4 of clock 1... Passed.
[00:00:00] Testing register 5 of clock 1... Passed.
[00:00:00] Testing register 6 of clock 1... Passed.
[00:00:00] Testing register 7 of clock 1... Passed.
[00:00:00] Testing register 8 of clock 1... Passed.
[00:00:00] Testing register 9 of clock 1... Passed.
[00:00:00] Testing register 10 of clock 1... Passed.
[00:00:00] Testing register 11 of clock 1... Passed.
[00:00:00] Testing register 12 of clock 1... Passed.
[00:00:00] Testing register 13 of clock 1... Passed.
[00:00:00] Testing register 14 of clock 1... Passed.
[00:00:00] Testing register 15 of clock 1... Passed.
[00:00:00] Testing register 16 of clock 1... Passed.
[00:00:00] Testing register 17 of clock 1... Passed.
[00:00:00] Testing register 18 of clock 1... Passed.
[00:00:00] Testing register 19 of clock 1... Passed.
[00:00:00] Testing register 20 of clock 1... Passed.
[00:00:00] Clock 1
[00:00:00] Passed
[00:00:00] Testing register 0 of clock 2... Passed.
[00:00:00] Testing register 1 of clock 2... Passed.
[00:00:00] Testing register 2 of clock 2... Passed.
[00:00:00] Testing register 3 of clock 2... Passed.
[00:00:00] Testing register 4 of clock 2... Passed.
[00:00:00] Testing register 5 of clock 2... Passed.
[00:00:00] Testing register 6 of clock 2... Passed.
[00:00:00] Testing register 7 of clock 2... Passed.
[00:00:00] Testing register 8 of clock 2... Passed.
[00:00:00] Testing register 9 of clock 2... Passed.
[00:00:00] Testing register 10 of clock 2... Passed.
[00:00:00] Testing register 11 of clock 2... Passed.
[00:00:00] Testing register 12 of clock 2... Passed.
[00:00:00] Testing register 13 of clock 2... Passed.
[00:00:00] Testing register 14 of clock 2... Passed.
[00:00:00] Testing register 15 of clock 2... Passed.
[00:00:00] Testing register 16 of clock 2... Passed.
[00:00:00] Testing register 17 of clock 2... Passed.
[00:00:00] Testing register 18 of clock 2... Passed.
[00:00:00] Testing register 19 of clock 2... Passed.
[00:00:00] Testing register 20 of clock 2... Passed.
[00:00:00] Clock 2
[00:00:02] Passed
[00:00:02] Testing register 0 of clock 3... Passed.
[00:00:02] Testing register 1 of clock 3... Passed.
[00:00:02] Testing register 2 of clock 3... Passed.
[00:00:02] Testing register 3 of clock 3... Passed.
[00:00:02] Testing register 4 of clock 3... Passed.
[00:00:02] Testing register 5 of clock 3... Passed.
[00:00:02] Testing register 6 of clock 3... Passed.
[00:00:02] Testing register 7 of clock 3... Passed.
[00:00:02] Testing register 8 of clock 3... Passed.
[00:00:02] Testing register 9 of clock 3... Passed.
[00:00:02] Testing register 10 of clock 3... Passed.
[00:00:02] Testing register 11 of clock 3... Passed.
[00:00:02] Testing register 12 of clock 3... Passed.
[00:00:02] Testing register 13 of clock 3... Passed.
[00:00:02] Testing register 14 of clock 3... Passed.
[00:00:02] Testing register 15 of clock 3... Passed.
[00:00:02] Testing register 16 of clock 3... Passed.
[00:00:02] Testing register 17 of clock 3... Passed.
[00:00:02] Testing register 18 of clock 3... Passed.
[00:00:02] Testing register 19 of clock 3... Passed.
[00:00:02] Testing register 20 of clock 3... Passed.
[00:00:02] Clock 3
[00:00:02] Passed
[00:00:02] SOC PWR Start Complete
[00:00:02] SOC RST Begin
[00:00:02] Current BootMode is set to DSP No-Boot
[00:00:02] SOC RST Complete
[00:00:02] BOOT COMPLETE

[00:00:03] Error: SOC_POWER_GOOD signal has de-asserted. Shutting down soc power.

[00:00:03] Full Reset Begin
[00:00:03] Full Reset Complete
[00:00:03] POR Begin
[00:00:03] POR Complete
[00:00:03] SOC PWR Stop Begin
[00:00:04] SOC PWR Stop Complete