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Synchronization of MCBSP Frame Sync on an external source

We have a question on the MCBSP bus for C6655 and C6657 DSP.

 

We would like our MCBSP0 frame sync of 48KHz to synchronize on a signal that comes in from an external source connected to the pin of MCBSP1 frame sync, which is 1 Hz. The solution we came up with is to configure MCBSP1 frame sync as an interrupt-able GPIO pin, have the MCBSP0 frame sync synchronized on a certain timer, and adjust the frequency of this timer if it doesn't exactly match the 1-second duration.

 

I have read about the frame sync signals and leaned that they can be configured as interrupt driven. We normally derive the MCBSP0 frame sync from the BCLK signal, which is an 24.5MHz external clock in our design. I also read about the timers and how we can read their value at every 1 Hz from the external source to detect clock drifts.

 

What's still not clear for me is how to adjust the MCBSP0 frame sync once the clock drift is detected. We can possibly make the frame sync to be derived by the system clock, but I haven't found out how to make it go a bit slower or faster depending on the detected offset.

 

I wonder if you have an idea how we can achieve this. Any inputs would be appreciated. Thank you

  • Hi TI Lady,
    We are working on this post. We will get back to you shortly or early next week with our inputs if any. Thank you for your patience.
  • Hi,

    Thanks for your post.

    May be, you could try McBSP Digital Loopback example( MCBSP_DigLpbkExampleProject) below is available in MCSDK package, Please refer this example and explore options if any to adjust McBSP framesync rate to bit slower or faster which would be my first recommendation

    MCSDK Path: "\ti\pdk_C6657_1_1_2_6\packages\ti\drv\exampleProjects\MCBSP_DigLpbkExampleProject"

    Also, Data frame synchronization can be independently programmable for the receiver and the transmitter for all data delay values. For more info. to program customized framesync generation through frameperiod (FPER) and framewidth (FWID), kindly refer section 2.5.4 from the keystone McBSP user guide as below:

    http://www.ti.com/lit/ug/spruhh0/spruhh0.pdf

    Thanks & regards,

    Sivaraj K

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  • We are quite familiar with the MCBSP example as we built our application based on this example code. I wonder if I set the clock source to internal, can I change the value of “srgrInputFreq” slightly without the need to reset MCBSP bus? If the change is within +-10% of this number, will there be a hit on the audio?

    Our audio bit clock is 24.576000Mhz.

     

    mcbspSrgParams.srgrInputFreq = 166666667; /* 166.67 MHz - SYSCLK6 */

    thoughts?

  • Any comment on this one?