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TSIP and TSIP_testProject

Aleksandr Lisovich
Intellectual 325 points

Hi All,

I am trying to run the TSIP_testProject on C6678 EVM evaluation board using CCS 5.2.

I don't have an AMC chassis so I amusing my own generator to supply CLK to TDM_CLCA P/N and Fsync to TDM_CLKC P/N through the AMC connector. The signal timing diagram is shown below. The CLC is 16.384MHz and Fsync has an active low level and the active level length of 1.5 clock periods. Fsync repeats every 1024 clock periods. Before running the TSIP_testProject I have verified that the differential clock and Fsync are present at the input of the level shift circuitry  (FPGA). The TSIP_testProject I am using is located at ..\pdk_C6678_1_1_2_5\packages\ti\drv\tsip\...

Unfortunately the test fails with various results  with the typical output also shown at the end of this post.

So my questions are:

1. Are the signals I supply to the C6678  EVM have the correct parameters like polarity, shift between clock and Fsyns, the correct number of clock periods between Fsync etc.

2. Do I need to make extra connections on the AMC and/or I need to supply some another signals?

Thank you,

Alex

[C66xx_0] **************************************************
[C66xx_0] ********** TSIP Test Start ***********************
[C66xx_0] **************************************************
[C66xx_0] Verify TSIP Port 0 data transfer...
[C66xx_0] -->Slot 0 TSIP data transfer verfication failed.
[C66xx_0] Before failing, verified 17 samples.
[C66xx_0] tsipToAppBuf[40]=0x0 when it should have been 0x41
[C66xx_0] -->Slot 1 TSIP data transfer verfication failed. Array tsipToAppBuffer is empty.
[C66xx_0] -->Slot 2 TSIP data transfer verfication failed. Array tsipToAppBuffer is empty.
[C66xx_0] -->Slot 3 TSIP data transfer verfication failed. Array tsipToAppBuffer is empty.
[C66xx_0] -->Slot 4 TSIP data transfer verfication failed. Array tsipToAppBuffer is empty.
[C66xx_0] -->Slot 5 TSIP data transfer verfication failed.
[C66xx_0] Before failing, verified 1 samples.
[C66xx_0] tsipToAppBuf[26]=0x0 when it should have been 0x33
[C66xx_0] -->Slot 6 TSIP data transfer verfication failed.
[C66xx_0] Before failing, verified 1 samples.
[C66xx_0] tsipToAppBuf[26]=0x0 when it should have been 0x33
[C66xx_0] -->Slot 7 TSIP data transfer verfication failed. Array tsipToAppBuffer is empty.
[C66xx_0] -->Slot 8 TSIP data transfer verfication failed. Array tsipToAppBuffer is empty.
[C66xx_0] -->Slot 9 TSIP data transfer verfication failed.
[C66xx_0] Before failing, verified 1 samples.
[C66xx_0] tsipToAppBuf[26]=0x0 when it should have been 0x33
[C66xx_0] -->Slot 10 TSIP data transfer verfication failed.
[C66xx_0] Before failing, verified 1 samples.
[C66xx_0] tsipToAppBuf[26]=0x0 when it should have been 0x33
[C66xx_0] -->Slot 11 TSIP data transfer verfication failed. Array tsipToAppBuffer is empty.
[C66xx_0] -->Slot 12 TSIP data transfer verfication failed.
[C66xx_0] Before failing, verified 1 samples.
[C66xx_0] tsipToAppBuf[103]=0x0 when it should have been 0x81
[C66xx_0] -->Slot 13 TSIP data transfer verfication failed.
[C66xx_0] Before failing, verified 1 samples.
[C66xx_0] tsipToAppBuf[26]=0x0 when it should have been 0x33
[C66xx_0] -->Slot 14 TSIP data transfer verfication failed.
[C66xx_0] Before failing, verified 1 samples.
[C66xx_0] tsipToAppBuf[26]=0x0 when it should have been 0x33
[C66xx_0] -->Slot 15 TSIP data transfer verfication failed.
[C66xx_0] Before failing, verified 1 samples.
[C66xx_0] tsipToAppBuf[110]=0x0 when it should have been 0x85
[C66xx_0] -->Slot 16 TSIP data transfer verfication failed.
[C66xx_0] Before failing, verified 1 samples.
[C66xx_0] tsipToAppBuf[110]=0x0 when it should have been 0x85
[C66xx_0] -->Slot 17 TSIP data transfer verfication failed.
[C66xx_0] Before failing, verified 1 samples.
[C66xx_0] tsipToAppBuf[29]=0x0 when it should have been 0x36
[C66xx_0] -->Slot 18 TSIP data transfer verfication failed.
[C66xx_0] Before failing, verified 1 samples.
[C66xx_0] tsipToAppBuf[29]=0x0 when it should have been 0x36
[C66xx_0] -->Slot 19 TSIP data transfer verfication failed. Array tsipToAppBuffer is empty.
[C66xx_0] -->Slot 20 TSIP data transfer verfication failed.
[C66xx_0] Before failing, verified 1 samples.
[C66xx_0] tsipToAppBuf[236]=0x0 when it should have been 0x4
[C66xx_0] -->Slot 21 TSIP data transfer verfication failed.
[C66xx_0] Before failing, verified 1 samples.
[C66xx_0] tsipToAppBuf[29]=0x0 when it should have been 0x36
[C66xx_0] -->Slot 22 TSIP data transfer verfication failed.
[C66xx_0] Before failing, verified 1 samples.
[C66xx_0] tsipToAppBuf[29]=0x0 when it should have been 0x36
[C66xx_0] -->Slot 23 TSIP data transfer verfication failed.
[C66xx_0] Before failing, verified 1 samples.
[C66xx_0] tsipToAppBuf[236]=0x0 when it should have been 0x4
[C66xx_0] -->Slot 24 TSIP data transfer verfication failed.
[C66xx_0] Before failing, verified 1 samples.
[C66xx_0] tsipToAppBuf[35]=0x0 when it should have been 0x3c
[C66xx_0] -->Slot 25 TSIP data transfer verfication failed.
[C66xx_0] Before failing, verified 1 samples.
[C66xx_0] tsipToAppBuf[35]=0x0 when it should have been 0x3c
[C66xx_0] -->Slot 26 TSIP data transfer verfication failed.
[C66xx_0] Before failing, verified 1 samples.
[C66xx_0] tsipToAppBuf[35]=0x0 when it should have been 0x3c
[C66xx_0] -->Slot 27 TSIP data transfer verfication failed.
[C66xx_0] Before failing, verified 1 samples.
[C66xx_0] tsipToAppBuf[236]=0x0 when it should have been 0x4
[C66xx_0] -->Slot 28 TSIP data transfer verfication failed.
[C66xx_0] Before failing, verified 1 samples.
[C66xx_0] tsipToAppBuf[236]=0x0 when it should have been 0x4
[C66xx_0] -->Slot 29 TSIP data transfer verfication failed.
[C66xx_0] Before failing, verified 1 samples.
[C66xx_0] tsipToAppBuf[106]=0x0 when it should have been 0x81
[C66xx_0] -->Slot 30 TSIP data transfer verfication failed. Array tsipToAppBuffer is empty.
[C66xx_0] -->Slot 31 TSIP data transfer verfication failed. Array tsipToAppBuffer is empty.
[C66xx_0] TSIP Port 0 data transfer verfication FAILED
[C66xx_0] TSIP Test ended. Test Failed.

  • 0
    TI__Mastermind 28085 points

    Hi,

    I am not sure your external clock parameters are correct for TSIP testing. I will check with my hardware team and get back to you. Please refer the similar e2e thread:

    I have inserted the EVM to AMC chassis and tested the both TSIP examples, It is working fine. Please find the log of examples below.

    TSIP_exampleProject:

    [C66xx_0] **************************************************
******* TSIP Example Start ***********************
**************************************************
TSIP port 0 is powered up
TSIP driver instance successfully initialized 
TSIP port instance successfully initialized 
TSIP port 0 super frame interrupt is registered
Initialize application buffers before TSIP-APP transfer
Enabling TSIP timeslot TX 0 RX 0... 
TSIP timeslot TX 0 RX 0 successfully enabled 
TSIP data transfer...
Verify TSIP data transfer...
TSIP data transfer verfication passed 
TSIP example ended. Example passed.

    TSIP_testProject:

    [C66xx_6] ********** TSIP Test Start ***********************
[C66xx_0] ********** TSIP Test Start ***********************
[C66xx_1] ********** TSIP Test Start ***********************
[C66xx_2] ********** TSIP Test Start ***********************
[C66xx_3] ********** TSIP Test Start ***********************
[C66xx_4] ********** TSIP Test Start ***********************
[C66xx_5] ********** TSIP Test Start ***********************
[C66xx_7] ********** TSIP Test Start ***********************
[C66xx_0] TSIP Test ended. Test Passed with 128 logical time slots verified using 2 ports. 
[C66xx_1] TSIP Test ended. Test Passed with 128 logical time slots verified using 2 ports. 
[C66xx_2] TSIP Test ended. Test Passed with 128 logical time slots verified using 2 ports. 
[C66xx_3] TSIP Test ended. Test Passed with 128 logical time slots verified using 2 ports. 
[C66xx_4] TSIP Test ended. Test Passed with 128 logical time slots verified using 2 ports. 
[C66xx_5] TSIP Test ended. Test Passed with 128 logical time slots verified using 2 ports. 
[C66xx_6] TSIP Test ended. Test Passed with 128 logical time slots verified using 2 ports. 
[C66xx_7] TSIP Test ended. Test Passed with 128 logical time slots verified using 2 ports.

    Thanks,

     

     

  • 0 in reply to Ganapathi Dhandapani95
    Intellectual 325 points
    Hi Ganapathi,

    Thank you for your reply.

    When you contact the hardware team, can you please also verify that I do not need to make any other connections on AMC connector like connect data output with data input etc.? At the moment I have only four active lines on the connector: TDM_CLKA P/N (two wires) and TDM_CLKC P/N (two wires).

    Looking at your output on TSIP_testProject, I can see that you run the code on all 8 DSPs and I run it on a sincle Core 0. Should I also run it on all 8 cores?

    And just to be sure, I run the TSIP_testProject as is, without any code modifications.

    Regards,

    Alex
  • 0 in reply to Aleksandr Lisovich
    Intellectual 325 points

    Hi Ganapathi,

    Do you have any updates for us? Basically we are stuck and are waiting for your reply. The thread you referred to is very useful but does not provide the definitive information on CLK and Fsync timing diagram. It also discusses the modified TSIP_testProject, while I would like to start with unmodified one. To summarize again, we need:

    1. Could you post the correct timing diagram for CLK and Fsync, including how frequently Fsync should pulse (1024 or 2048 or else clocks)?

    2. Should we make extra connections on AMC connector apart from TDM_CLKA P/N (two wires) and TDM_CLKC P/N (two wires), like connect the RTx with DRx etc?

    3. Should we make any modifications to TSIP_testProject (I hope not)?

    You response is greatly appreciated

    Regards , 

    Alex