Hi,
I'm working on a C6678 to set up a DMA transfer triggered by a GPINT, more precisely by GPINT12. As exhaustively described in
http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/467313/1678176
this event cannot directly trigger a DMA transfer and needs to be routed through a CIC in order to reach a DMA channel controller; e.g. one could map system interrupt 4 (see table 7-40 of C6678 datasheet) to host interrupt 0 an then enable event 42 (CIC2_OUT0) of EDMACC1 (see table 7-36).
A problem arises if an A-sync DMA transfer is needed, where every GPINT12 (routed through CIC2) is intended to start the trasfer of ACNT bytes: the host interrupt status bit (ENA_STATUS_REG, see CIC user guide section 2.2.12) must be manually cleared after each event; otherwise, the CIC won't generate the next event for the DMA controller, even if a GPINT12 occurs. Indeed I've been able to transfer only the first ACNT bytes so far; in my case BCNT=4096 and CCNT=1, therefore the remaining 4095 transfers never occur. One could make use of the Intermediate Transfer Completion feature to force an interrupt after every single event to clear the CIC host interrupt status bit, but the CPU would get interrupted too many times and too frequently, defeating the purpose of using DMA.
I'd like to hear some opinions about this. Does anyone see alternative solutions?
Thanks
Davide