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Keystone ECC feature in ECC parity RAM

Thomas Yang55737
Expert 4566 points

hI experts,

If there is a soft bit error ocurred in ECC parity RAM,  Can ECC report the error result on this? What does ECC module to do in this error case?

There is no description on TI userguide on this.

Thanks

Thomas

  • 0
    TI__Mastermind 43955 points
    Hi Thomas,

    For Keystone - II devices, in u-boot source , implementation of DDR3 ECC is available. You can refer to that code for understanding the ECC initialization and configuration.

    For DDR3, in uboot, we have the following command to check the ecc errors as a part of DDR testing.

    Usage:
    ddr ecc_err <addr in hex> <bit_err in hex> - generate bit errors in DDR data at <addr>, the command will read a 32-bit data from <add
    r>, and write (data ^ bit_err) back to <addr>
  • 0 in reply to Shankari G
    TI__Genius 12805 points

    You did not mention what device or what memory,  so I will give you a generic answer. You need to adapt it to your device and the memory that you are interested in

    When there is ECC error, usually an event/exception  bit is set.  The responsibility of the software is to decide what to do with this error.  Here is what usually needs to be done

    1. Look at the appropriate user guide or data-sheet of teh memory or access to the memory and find the event that you are looking for and what it is connected to. Look for example to chapter 2.6 of PRUGW7A - this gives you the interrupts that the MSMC generates when an error is detected or corrected

    2. Map the event to the CPU that you want to respond to the event. Look for example at SPRS691 at table 7-38 line 98, 99 to see what events are in the input of CIC. Then map it to the CPU using csl or bios functions

    3. Decide what you want to do when error occurs and develop ISR

    Ran

  • 0 in reply to ran35366
    TI__Expert 4566 points

    Thanks for the reply. I know the ECC/EDC process and solution for L1 L2 SL2 and DDR3, but what I ask is the case that the parity RAM met soft bit error, here parity RAM is the RAM which stores the parity bit internally, No released doc have this info.

    -Thomas

  • 0 in reply to Thomas Yang55737
    TI__Expert 4566 points

    Hi Experts,

    Do you have any updates on this?

    Thanks

    Thomas

  • 0 in reply to Thomas Yang55737
    TI__Genius 12805 points

    Thomas

    I am not sure what you are looking for.  Are you looking for the address of the memory where the error correction code is stored?

    Can you elaborate what you mean?  Which RAM you refer to? and what exactly are you looking for

    It may be a question for the hardware guys

    Thanks

    Ran