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CPRI problem with C6670

Hi,anyone :

     I have one broad on which there are one chip of C6670 DSP woking as REC equipment  and one chip of  altera FPGA (belonging to Cyclone V GT falimy) woking as RE equipment .The CPRI Bus is used to transfer data between each .

The project running in the DSP chip is downloaded from TI Web called"  AIF2 LTE TDD" ,

and within the FPGA , one serdes module as the physical layer + CPRI protocol module ( designed privately accordding to <CPRI_v_4_1_2009-02-18>,not IP Core) as logic layer .

During the test , i ( FPGA engineer ) found that ,  at FPGA ponit, link is built and and keep on , the anto-negotiate function is also done (local proticol parameter such as Ethernet Point and Protocol Version is changed by DSP ,not the initial value anymore), and also  radio / hyperframe/basic frame can be received and anylised by the private CPRI protocol module . But the payload is null .

at the DSP point , link is up ,RM/TM is in SYN state , no payload is received .

Can anyone give me some suggestion about this ? 

that is all ,thanks a lot !

                                                                      Rick

  • Welcome to the TI E2E forum. I hope you will find many good answers here and in the TI.com documents and in the TI Wiki Pages (for processor issues). Be sure to search those for helpful information and to browse for the questions others may have asked on similar topics (e2e.ti.com). Please read all the links below my signature.

    We will get back to you on the above query shortly. Thank you for your patience.

  • Difficult to diagnose with the information provided.  You say that both the RM Status Register and TM Status Register are in FRAME_SYNC mode?  Do the status registers show any errors?  What about the EE registers?  Does the AIF2 configuration of the 6670's project software match what the FPGA is providing? Is this CPRI Fast C&M, and if so, have you read the erratas (http://www.ti.com/lit/er/sprz332f/sprz332f.pdf, Usage Note 26) and conform to the workarounds?

  • thank you for your replying , and sorry for breaking off the communication in laset week .

    i have done some test to get the information that you suggested , the CCS tool said as following :

    link 4 runs at 2x rate, normal operation, LTE 20 MHz AxC, antenna data in AxC slot only
    link 5 is disabled
    Enable Exception handling...
    DDR_FDQ entry count = 0 (initial value 160)
    SL2_FDQ entry count = 160 (initial value 72)
    CORE3_LL2_FDQ entry count = 72 (initial value 9189736)
    ------------------status when test complete---------------------
    Ingress End Of Packet count = 0
    Egress End Of Packet count = 10978
    AT PHYT Frame= 13, Clock= 7897476
    AT RADT Frame= 13, Symbol= 112, Clock= 8354
    AT PHYT sync input is not aligned to the PHYT counter frame boundary.
    ----------------link 4 status----------------
    captured PI value = 0
    RM ST3 State FRAME_SYNC
    RM Number of Line Code Violations = 65535
    TM FSM in FRAME_SYNC state
    DDR_FDQ entry count = 0 (initial value 160)
    SL2_FDQ entry count = 160 (initial value 72)
    CORE3_LL2_FDQ entry count = 72 (initial value 9189736)
    Throughput of link 4 = 0 MB/s (0 good packets, 0 bad packets)
    Total throughput of AIF = 0 MB/s (0 good packets, 0 bad packets)

    and the EE registers information is at next :

      i am not good at DSP designnig process , so i do not know what is the main point during these messages ,please help , thank you !

      that is all , best regards to you !

                                                                                                                            Rick/

                                                                                                                           7th Dec.

  • Hi, I noticed a few things in the registers.  By the way, decimal format is rather difficult to use; hex is much better.

    First, there are a few issues on the Rx side: 1) The SD_Rx_Sts register (see table 8-11 in the AIF2 user guide) bits 9 and 10 indicate over/under equalizer  analysis.  This could mean issues with the connection to the FPGA.  The RM status registers also are showing line code (8b10b decoding) violations.

    Are you trying to send packets from AIF2 to the FPGA and have it loop them back to AIF2?  If you have visibility into data received by the FPGA you could enable the Tx test patterns (see table 8-13), and verify what is coming into the FPGA.  You should also look through the AIF2 configuration, primarily the SD, RM and TM modules and confirm it is compatible with your FPGA.  You can do this by examining the source code or dumping the registers and comparing their values to the user guide register descriptions.

  • thanks for your information , for the "over/under equalizer" eeror , i got less discreption during the "AIF2 introduce document" , and  think that once working , it should be over or under equalizer error found , hardly over and under equalizer error happend together .

    i have already done the external loopback experiment for DSP AIF2 working as CPRI protocol ,the path is  DSP TX--> FPGA serdes RX--> FGPA serdesTX --> DSP RX, and the applcaiton layer function in DSP project said that TX/RX  progress was all done and successful . Howerver  i look for the input datasream at the FPGA serdes rx poin , no coma data(K28.5 symbol)was found ,no certain payload is captured .

    So i ask my workmate to do the tx working only , i could find the coma data(K28.5 symbol) , and saw the whole hyperframe stucture / basic frame structure ,within the basic frame , the word1-word15 for the payload were regular , only word 1 and word9 changed in each basic frame ,others kept fixed value .

    For this , i was really pullzed , could you give me some word?  

    That is all ,Thanks .

                                                                                   Rick