Keystone II Hyperlink Rate to 10G

skyc0lour

Hi,

We are using hyperlink interface to 6.25g and would like to move to 10G however both pdk_keystone2_3_01_03_06 and pdk_keystone2_3_01_04_07 10G do not support this mode for 312.5MHz reference clock.

See attached screenshot taken from "C:\ti\pdk_keystone2_3_01_03_06\packages\ti\drv\hyplnk\example\common\hyplnkLLDIFace.c" for your reference.

Errata sheet for K2K/K2H does not reflect 10G issue.

Could you please confirm why this is unsupported?

Kind Regards,

Piyush

over 8 years ago

0 Ganapathi Dhandapani95 over 8 years ago

TI__Mastermind 28085 points

Hi,

K2K/K2H device will support 10G Hyperlink link rate.

MCSDK examples are based on TI EVM boards, two EVM boards are connected via Hyperlink cable for non-loopback mode testing. Due to the long cable(12 inches long), could only get a sustainable rate of 3.125Gbps. With another cable, managed to get a sustainable rate of 7.5Gbps.

If you using your own custom board, then you can modify the hyperlink test code for 10G line rate. MCSDK hyperlink driver will support all line rates.

Thanks,

0 skyc0lour over 8 years ago in reply to Ganapathi Dhandapani95

Intellectual 600 points

Hi Ganapathi,

Thank you for getting back to me. We did try this by modifying the code however we had a bring up reliability on the interface. Hence our team has decided to get support from TI. We can start investigating the problem but my guess would be drive strength between two devices could be a problem.

Do you know how drive strength parameter values are derived in MCSDK. Are they tested in any way and if so, Are they setup for long cable or a very short track (<2 inches) which is there on our custom board?

I have also looked at the user manual for serdes block here http://www.ti.com/lit/ug/spruho3b/spruho3b.pdf but struggling to understand this as there is no description for bit fields.

Kind Regards,

Piyush

0 Ganapathi Dhandapani95 over 8 years ago in reply to skyc0lour

TI__Mastermind 28085 points

Hi,

I have tested the Hyperlink example at 6.25Gbaud rate using 12 inches long cable. Some customers are tested the the Hyperlink example at higher rate on our custom board(two device internally connected on same board).

Please take a look at "hyplnkLLDCfg.h" file and modified the definitions to configure the Hyperlink peripheral, such as selecting the serial speed and loopbacks.

#define hyplnk_EXAMPLE_REFCLK_USE_PLATCFG
//#define hyplnk_EXAMPLE_REFCLK_156p25
//#define hyplnk_EXAMPLE_REFCLK_250p00
//#define hyplnk_EXAMPLE_REFCLK_312p50

/*****************************************************************************
 * Select internal loopback or use the SERDES connection
 *****************************************************************************/
//#define hyplnk_EXAMPLE_LOOPBACK

/*****************************************************************************
 * Select number of lanes allowed
 *****************************************************************************/
//#define hyplnk_EXAMPLE_ALLOW_0_LANES
//#define hyplnk_EXAMPLE_ALLOW_1_LANE
#define hyplnk_EXAMPLE_ALLOW_4_LANES

/*****************************************************************************
 * Select a serial rate
 *****************************************************************************/
//#define hyplnk_EXAMPLE_SERRATE_01p250
#define hyplnk_EXAMPLE_SERRATE_03p125
//#define hyplnk_EXAMPLE_SERRATE_06p250
//#define hyplnk_EXAMPLE_SERRATE_07p500
//#define hyplnk_EXAMPLE_SERRATE_10p000
//#define hyplnk_EXAMPLE_SERRATE_12p500

Hyperlink user guide manual have limited serdes configuration values only. It will be updated on next release. Please refer the "hyplnkLLDIFace.c" file for all serial rate PLL & SERDES configuration.

#elif defined(hyplnk_EXAMPLE_SERRATE_10p000)
  #define hyplnk_EXAMPLE_VUSR_TX_TWPST1   20 /* -10% */
  #define hyplnk_EXAMPLE_VUSR_TX_TWPRE    1  /* -10.0% */
  #define hyplnk_EXAMPLE_VUSR_TX_SWING    0x8

  /* full rate implies MPY*4 below, vrange is 0 since 10.0*0.25 > 2.17 */
  #define hyplnk_EXAMPLE_VUSR_PLL_VRANGE  0
  #define hyplnk_EXAMPLE_VUSR_RX_RATE     0  /* full rate */
  #define hyplnk_EXAMPLE_VUSR_TX_RATE     0  /* full */

  #if defined(hyplnk_EXAMPLE_REFCLK_156p25)
    #define hyplnk_EXAMPLE_VUSR_PLL_MPY    80 /* MPY in 0.25 units = 16x */
                                              /* 16*4 * 156.25 = 10.0G */
  #elif defined(hyplnk_EXAMPLE_REFCLK_250p00)
    #define hyplnk_EXAMPLE_VUSR_PLL_MPY    40 /* MPY in 0.25 units = 10x */
                                              /* 10*4 * 250 = 10.0G */
  #elif defined(hyplnk_EXAMPLE_REFCLK_312p50)
    #define hyplnk_EXAMPLE_VUSR_PLL_MPY    32 /* MPY in 0.25 units = 8x */
                                              /* 8*4 * 312.5 = 10.0G */
  #endif

Thanks,

0 skyc0lour over 8 years ago in reply to Ganapathi Dhandapani95

Intellectual 600 points

Hi Ganapathi,

I have tried playing with them in the past but they do not get used.

Hyperlink example for K2H and K2K do not use those definitions at all such as TWPST1, TWPRE, SWING etc instead code path goes straight to serdes configuration in CSL and that contains just numbers and no description.

See below where drive strength definitions are not used.

This is what gets called on K2H/K2K processors.

Kind Regards,

Piyush N. Prince

0 skyc0lour over 8 years ago in reply to skyc0lour

Intellectual 600 points

Hi Ganapathi,

Do you have any feedback on my last response?

Kind Regards,

Piyush

0 Mike Farley over 8 years ago in reply to skyc0lour

TI__Prodigy 735 points

Dear Ganapathi,

Thanks in advance for helping us here.
Mike Farley, Account Mgr

0 Ganapathi Dhandapani95 over 8 years ago in reply to Mike Farley

TI__Mastermind 28085 points

Hi,

I will check with development team and get back to you.

Thanks,

0 skyc0lour over 8 years ago in reply to Ganapathi Dhandapani95

Intellectual 600 points

Appreciate your help Ganapathi.

Regards,

Piyush

0 lding over 8 years ago in reply to skyc0lour

TI__Guru* 95265 points

Piyush,

The KS II device supports Hyperlink up to 10.0Gb/s * 4 lanes. The swing, twpre, twpst1 are parameters for KS I device and don't apply to KS II.

For KS II, the Tx parameters are C1, C2, CM, TX_ATT and VREG, Rx side parameters are RX_ATT and BOOST. For Rx side, those two parameters can be adapted from receiver or forced, if you run at a higher rate (e.g 10Gb/s), force with a fixed value is recommended. Those Tx/Rx parameters are described in http://www.ti.com/lit/ug/spruho3b/spruho3b.pdf.

Need some info for your setup: is this KS II to KS II connection on your customized board? trace is ~ 2 inchs? Did you get any reliability issue when run 6.25 Gb/s? What is your reference clock (312.5MHz or 156.25MHz)? Did you do any BER sweep test to determine the best setting of Tx/Rx parameters? You running MCSDK example on DSP core? not ARM core, not running Linux Hyperlink driver, correct?

Regards, Eric

0 skyc0lour over 8 years ago in reply to lding

Intellectual 600 points

Hi Eric,

Thank you for your response.

Our setup is:
KSII (K2K) to KSI (C6678).
Reference frequency is 312.5 to both chip (one source).
Trace length is ~1" for DSP1 and 3" for DSDP2 - We have KSII (DSP0) port 1 to KSI (DSP1) and KSII (DSP0) port 1 to KSI (DSP2)
We did not sweep BER. Not sure how to do it on KSI.
We are running LLD example from DSP and not from ARM/Linux.

Kind Regards,

Piyush

0 lding over 8 years ago in reply to skyc0lour

TI__Guru* 95265 points

Is the 6.25Gb/s link stable? How do you test the reliablility? Power cycle test? How the code is loaded and run? Do you have some flash/bootloder so everything is automated for power cycle test or you use JATG/CCS?

Regards, Eric

0 skyc0lour over 8 years ago in reply to lding

Intellectual 600 points

Hi Eric,

We perform two kind of tests. Power cycle test (4 - days) and Stress test (4 - days continues data transfer from all direction). Please note during this time card is being thermal cycled from 0 to 45 degree C (DSP temperature 10 to 80)
- PWC test has a start up issue 1 in 120 power cycles
- STRESS test has no reliability issue.
Code is fully automated.
- DSP0 - we use mpmcl from ARM/LINUX to load it.
- DSP1/2 - we use EMAC bootling

Kind Regards,

Piyush

0 lding over 8 years ago in reply to skyc0lour

TI__Guru* 95265 points

What you mean:

DSP0 - we use mpmcl from ARM/LINUX to load it.

DSP1/2 - we use EMAC bootling

Do you mean 1 K2H is connected to 2 C6678 via Hyperlink ports 0 and 1. So DSP 0 is K2H, DSP1 and DSP2 is two C6678 respectively? Power cycle test has a failure rate of 1/120? What is your failure definition? failure means Hyperlink read from remote and get stuck? Or you use some registers to determine the link failed before trying to read from remote?

Then move to 10Gb/s, as you know the MCSDK code doesn't have 10G example, but you can change those #if , #else, #if .... to add the 10G support there. The code change should be straightforward, you need to make sure below will be called:

if (ref_clock == CSL_SERDES_REF_CLOCK_312p5M && rate == CSL_SERDES_LINK_RATE_10G)

{

csl_wiz8_sb_refclk312p5MHz_20bit_10Gbps_sr1(base_addr);

}

Then, you said reliability issue. Do you mean the link is never come up at all? Or sometimes come up, sometimes fails? Or you see accumulating ECC error over time? I need details.

Do you have any debug capability into this issue by CCS/JTAG? I want you to collect some memory dump for further analysis?

Regards, Eric

0 skyc0lour over 8 years ago in reply to lding

Intellectual 600 points

Hi Eric,

Good questions. Your assumption about PORT connection and DSP ids are all correct.

Regarding 6.25G failures (1 in 120 power cycles):

Our SW (based on LLD example) checks for LinkStatus and Status register as below.

while ((!status.link) || (status.serialHalt) || (status.pllUnlock) || ((linkStatus.raw & 0x21002000) != 0x21002000));

When we get failure: Link status register of DSP1/2 is 0xfdf00cf5 or 0xfdf00cf8 and DSP0 is 0xfdf0bdf3. This is a failure condition for us.

When we moved to 10G, we faced quite a high link up error. 1 in 5 so we did not do full long term test.

Yes i can run CCS example using emulator so there is no issue for getting memory dump for you.

Kind Regards,

Piyush

0 lding over 8 years ago in reply to skyc0lour

TI__Guru* 95265 points

Piyush,

"while ((!status.link) || (status.serialHalt) || (status.pllUnlock) || ((linkStatus.raw & 0x21002000) != 0x21002000));

In our code we don't have condition checking of (linkStatus.raw & 0x21002000) != 0x21002000, I guess that you added by yourself. This linkStatus register is very important to determine the usefulness of the link, our example code should add check before declaring the link is up.

The upper 16 bits of the link status register on a device indicates the Tx state of the link on this device.
The upper 16 bits should be B’1x1x11011111xxxx where x is any value.
TxLinked == (LinkRegisterValue&0xadf00000)== 0xadf00000;
Be carefull, the last 4-bits indicate polarity and may be different on different links and boards.

The Lower 16 bits of the link status register on a device indicates the Rx state of the link on this device.
The lower 16 bits should be B’1x1x11011111xxxx where x is any value.
RxLinked == (LinkRegisterValue&0x0000adf0)== 0x0000adf0;
Be carefull, the last 4-bits indicate polarity and may be different on different links and boards.

In most of the system design, 4 lanes are used and the Tx/Rx pair polarity are the same along the trace for all 4 lanes, so linkStatus = 0xfdf0_bdf0. You can use this condition for the link check.

"DSP1/2 is 0xfdf00cf5 or 0xfdf00cf8 and DSP0 is 0xfdf0bdf3" ====> all of those indicating Rx side error. Given Tx and Rx is a pair, if DSP1/2 is 0xfdf00cf5/8 (Rx error), then I bet the DSP0 side would be Tx side error with link status like 0xccf0bdf0. I don't think it can happen both link pantners are Rx error. When you have register dump, we will see.

The dump I need is: several failure cases and a working case (you can use either 6.25G or 10.0G test):
K2H side:
- hyperlink 0x2140_0000 to 0x2140_007c for port 0;
- hyperlink 0x2140_0100 to 0x2140_017c for port 1;
- 0x231_bfe0 to 0x231_bffc for port 0;
- 0x231_dfe0 to 0x231_dffc for port 1;

C6678:
- hyperlink 0x2140_0000 to 0x2140_007c

Regards, Eric

0 skyc0lour over 8 years ago in reply to lding

Intellectual 600 points

Hi Eric,

Apologies for taking a little bit longer. I should be able to get you some numbers tomorrow.

Kind Regards,

Piyush

0 skyc0lour over 8 years ago in reply to skyc0lour

Intellectual 600 points

Hi Eric,

I have attached memory dump as requested for working case for 10G.

I will post failing case asap.

Kind Regards,

Piyush

k2k_dsp0_0x0231dfe0.dat

k2k_dsp0_0x21400000.dat

k2k_dsp0_0x21400100.dat

k2k_dsp1_0x21400000.dat

k2k_dsp2_0x21400000.dat

k2k_dsp0_0x0231bfe0.dat

0 lding over 8 years ago in reply to skyc0lour

TI__Guru* 95265 points

Piyush,

In the working 10G case, why offset 0x58 LinkStatus = 0xFDF0BDF1/3/5/A? The bit 3-0 indicated lane polarity reversal when not 0. Is this intended in PCB design? For the working 6.25G, is the same lane polarity reversal observed?

Regards, Eric

0 skyc0lour over 8 years ago in reply to lding

Intellectual 600 points

Hi Eric,

Lane reversal is constant on both 6.25G and 10G. Schematics has lane reversal on PORT0 of DSP0 (RX side (0-0, 3-1, 1-2, 2-3) and Tx Side (0-0, 1-1, 3-2, 2-3) and on PORT1 of DSP0 (RX side(no reversal) and TX side (0-0, 2-1, 1-2, 3-3)).

Kind Regards,

Piyush

0 lding over 8 years ago in reply to skyc0lour

TI__Guru* 95265 points

Thanks! Waiting for you to collect a few failure case dumps.

Regards, Eric

0 skyc0lour over 8 years ago in reply to lding

Intellectual 600 points

Hi Eric,

I have managed to capture fail condition where hard errors are triggered not the link status one. I will carry on doing further testing until i get some link up errors.

Error condition: Hard error on DSP0 Hyperlink PORT1 this is connected to DSP1.

Trace: I had to use our automated system hence dump is in slightly different format.

Kind Regards,

Piyush

c6678_dsp1_no_error.txt

Welcome to CommAgility Telnet Interface.
B:AMC-D24A4-RF4 (c) CommAgility Ltd.
D:1 PRODTEST V1.1.0 Feb 23 2016 17:14:58

K7:0x24a4 IMG:0x0005 GLUE:0x0003

Enter '?' or 'help' for a list of commands.
Active connection : 10.10.12.20:51199

CA> dspteststart 1 0x51 1 1
Test command 0x0051 sent to CORE 1
CA> dsptestdump 1 1
CAD1:Performing Card Init
Waiting for Test Command
HYP_slavetest:DSP:1:
HYP_slavetest:DSP:1: Pass Running Hyperlink at 10G
HYP_slavetest:DSP:1: Version #: 0x01000105; string HYPLNK LLD Revision: 01.00.01
.05:Nov 19 2012:16:04:15
HYP_slavetest:DSP:1:About to do system setup (PLL, PSC, and DDR)
HYP_slavetest:DSP 1:
&&
CA> dsptestdump 1 1
CAD1:HYP_slavetest:DSP 1: Constructed SERDES configs: PLL=0x00000040; RX=0x0046c
485; TX=0x000d2b05
HYP_slavetest:DSP:1: system setup worked
HYP_slavetest:DSP:1: About to set up HyperLink Peripheral
HYP_slavetest:DSP 1:
HYP_slavetest:DSP 1: ======== begin registers before initialization ========
HYP_slavetest:DSP 1:
HYP_slavetest:DSP 1: Revision register contents:
  Raw    = 0x4e901900
HYP_slavetest:DSP 1:
HYP_slavetest:DSP 1: Status register contents:
  Raw        = 0x04400005
HYP_slavetest:DSP 1:
HYP_slavetest:DSP 1: Link status register contents:
  Raw       = 0xfdf0bdfa
HYP_slavetest:DSP 1:
HYP_slavetest:DSP 1: Control register contents:
  Raw             = 0x00000000
HYP_slavetest:DSP 1:
HYP_slavetest:DSP 1: Control register contents:
  Raw        = 0x0000000&&
CA> dsptestdump 1 1
CAD1:0
HYP_slavetest:DSP 1: ========= end registers before initialization =======
HYP_mastertest:DSP:1: Checking for Corrected and Non-corrected errors
HYP_slavetest:DSP 1:
HYP_slavetest:DSP 1: SERDES_STS (32 bits) contents: 0x0c183061; lock = 1
HYP_slavetest:DSP 1: ====== begin registers after initialization =======
HYP_slavetest:DSP 1:
HYP_slavetest:DSP 1: Status register contents:
  Raw        = 0x04400005
HYP_slavetest:DSP 1:
HYP_slavetest:DSP 1: Link status register contents:
  Raw       = 0xfdf0bdfa
HYP_slavetest:DSP 1:
HYP_slavetest:DSP 1: Control register contents:
  Raw             = 0x00006200
HYP_slavetest:DSP 1: ===== end registers after initialization ======
HYP_slavetest:DSP 1: Waiting 5 seconds to check link stability
HYP_mastertest:DSP:1: Checking&&
CA> dsptestdump 1 1
CAD1: for Corrected and Non-corrected errors
HYP_mastertest:DSP:1: Checking for Corrected and Non-corrected errors
HYP_slavetest:DSP 1: Link seems stable
HYP_slavetest:DSP 1: About to try to read remote registers
HYP_mastertest:DSP:1: Checking for Corrected and Non-corrected errors
HYP_slavetest:DSP 1: ======== begin REMOTE registers after initialization ======
HYP_slavetest:DSP 1:
HYP_slavetest:DSP 1: Status register contents:
  Raw        = 0x0440000b
HYP_slavetest:DSP 1:
HYP_slavetest:DSP 1: Link status register contents:
  Raw       = 0xfdf0bdf3
HYP_slavetest:DSP 1:
HYP_slavetest:DSP 1: Control register contents:
  Raw             = 0x00006200
HYP_slavetest:DSP 1: ======== end REMOTE registers after initialization ======
HYP_slavetest:DSP:1: Running at 10G
HY&&
CA> dsptestdump 1 1
CAD1:P_slavetest:DSP:1: Link Speed is 4 * 10.0 Gbps
HYP_slavetest:DSP:1: Peripheral setup worked
hyplnkExampleAddrMap:DSP 1:
&&
CA> dsptestdump 1 1
Nothing to dump, testlog empty
CA> dsptestdump 1 1
Nothing to dump, testlog empty
CA> mr 0x21400000 10
0x21400000 -> 0x4e901900
0x21400004 -> 0x00006200
0x21400008 -> 0x04400005
0x2140000c -> 0x80000000
0x21400010 -> 0x00000000
0x21400014 -> 0x00000000
0x21400018 -> 0x00000000
0x2140001c -> 0x00000c0b
0x21400020 -> 0x00000000
0x21400024 -> 0x00000000
0x21400028 -> 0x00000000
0x2140002c -> 0x00000c06
0x21400030 -> 0x00000000
0x21400034 -> 0x00000000
0x21400038 -> 0x00000000
0x2140003c -> 0x11800015
CA> mr 0x21400040 10
0x21400040 -> 0x0001009e
0x21400044 -> 0x0707000c
0x21400048 -> 0x00000000
0x2140004c -> 0x00000000
0x21400050 -> 0x00000000
0x21400054 -> 0x00000000
0x21400058 -> 0xfdf0bdfa
0x2140005c -> 0x00000000
0x21400060 -> 0x00000000
0x21400064 -> 0x00000000
0x21400068 -> 0x00000000
0x2140006c -> 0x00000000
0x21400070 -> 0xffff0000
0x21400074 -> 0x00000000
0x21400078 -> 0x00000000
0x2140007c -> 0x00000000
CA>

c6678_dsp2_no_error.txt

Welcome to CommAgility Telnet Interface.
B:AMC-D24A4-RF4 (c) CommAgility Ltd.
D:2 PRODTEST V1.1.0 Feb 23 2016 17:14:58

K7:0x24a4 IMG:0x0005 GLUE:0x0003

Enter '?' or 'help' for a list of commands.
Active connection : 10.10.12.20:51200

CA> dspteststart 2 0x51 1 1
Test command 0x0051 sent to CORE 2
CA> dsptestdump 2 1
CAD2:Performing Card Init
Waiting for Test Command
HYP_slavetest:DSP:2:
HYP_slavetest:DSP:2: Pass Running Hyperlink at 10G
HYP_slavetest:DSP:2: Version #: 0x01000105; string HYPLNK LLD Revision: 01.00.01
.05:Nov 19 2012:16:04:15
HYP_slavetest:DSP:2:About to do system setup (PLL, PSC, and DDR)
HYP_slavetest:DSP 2:
&&
CA> dsptestdump 2 1
CAD2:HYP_slavetest:DSP 2: Constructed SERDES configs: PLL=0x00000040; RX=0x0046c
485; TX=0x000d2b05
HYP_slavetest:DSP:2: system setup worked
HYP_slavetest:DSP:2: About to set up HyperLink Peripheral
HYP_slavetest:DSP 2:
HYP_slavetest:DSP 2: ======== begin registers before initialization ========
HYP_slavetest:DSP 2:
HYP_slavetest:DSP 2: Revision register contents:
  Raw    = 0x4e901900
HYP_slavetest:DSP 2:
HYP_slavetest:DSP 2: Status register contents:
  Raw        = 0x04400085
HYP_slavetest:DSP 2:
HYP_slavetest:DSP 2: Link status register contents:
  Raw       = 0xfdf0bdf5
HYP_slavetest:DSP 2:
HYP_slavetest:DSP 2: Control register contents:
  Raw             = 0x00000000
HYP_slavetest:DSP 2:
HYP_slavetest:DSP 2: Control register contents:
  Raw        = 0x0020000&&
CA> dsptestdump 2 1
CAD2:1
HYP_slavetest:DSP 2: ========= end registers before initialization =======
HYP_mastertest:DSP:2: Checking for Corrected and Non-corrected errors
HYP_slavetest:DSP 2:
HYP_slavetest:DSP 2: SERDES_STS (32 bits) contents: 0x0c183061; lock = 1
HYP_slavetest:DSP 2: ====== begin registers after initialization =======
HYP_slavetest:DSP 2:
HYP_slavetest:DSP 2: Status register contents:
  Raw        = 0x04400005
HYP_slavetest:DSP 2:
HYP_slavetest:DSP 2: Link status register contents:
  Raw       = 0xfdf0bdf5
HYP_slavetest:DSP 2:
HYP_slavetest:DSP 2: Control register contents:
  Raw             = 0x00006200
HYP_slavetest:DSP 2: ===== end registers after initialization ======
HYP_slavetest:DSP 2: Waiting 5 seconds to check link stability
HYP_mastertest:DSP:2: Checking&&
CA> dsptestdump 2 1
CAD2: for Corrected and Non-corrected errors
HYP_mastertest:DSP:2: Checking for Corrected and Non-corrected errors
HYP_slavetest:DSP 2: Link seems stable
HYP_slavetest:DSP 2: About to try to read remote registers
HYP_mastertest:DSP:2: Checking for Corrected and Non-corrected errors
HYP_mastertest:DSP:2: Pass Remote after stability wait status.rError = 1
HYP_mastertest:DSP:2: Fail Errors Detected, see print messages above
HYP_slavetest:DSP 2: ======== begin REMOTE registers after initialization ======
HYP_slavetest:DSP 2:
HYP_slavetest:DSP 2: Status register contents:
  Raw        = 0x0440010b
HYP_slavetest:DSP 2:
HYP_slavetest:DSP 2: Link status register contents:
  Raw       = 0xfdf0bdf1
HYP_slavetest:DSP 2:
HYP_slavetest:DSP 2: Control register contents:
  Raw &&
CA> dsptestdump 2 1
CAD2:            = 0x00006200
HYP_slavetest:DSP 2: ======== end REMOTE registers after initialization ======
HYP_slavetest:DSP:2: Running at 10G
HYP_slavetest:DSP:2: Link Speed is 4 * 10.0 Gbps
HYP_slavetest:DSP:2: Peripheral setup worked
hyplnkExampleAddrMap:DSP 2:
&&
CA> dsptestdump 2 1
Nothing to dump, testlog empty
CA> mr 0x21400000 10
0x21400000 -> 0x4e901900
0x21400004 -> 0x00006200
0x21400008 -> 0x04400005
0x2140000c -> 0x80000000
0x21400010 -> 0x00000000
0x21400014 -> 0x00000000
0x21400018 -> 0x00000000
0x2140001c -> 0x00000c0b
0x21400020 -> 0x00000000
0x21400024 -> 0x00000000
0x21400028 -> 0x00000000
0x2140002c -> 0x00000c06
0x21400030 -> 0x00000000
0x21400034 -> 0x00000000
0x21400038 -> 0x00000000
0x2140003c -> 0x12800015
CA> mr 0x21400040 10
0x21400040 -> 0x0001009e
0x21400044 -> 0x0707000c
0x21400048 -> 0x00000000
0x2140004c -> 0x00000000
0x21400050 -> 0x00000000
0x21400054 -> 0x00000000
0x21400058 -> 0xfdf0bdf5
0x2140005c -> 0x00000000
0x21400060 -> 0x00000000
0x21400064 -> 0x00000000
0x21400068 -> 0x00000000
0x2140006c -> 0x00000000
0x21400070 -> 0xffff0000
0x21400074 -> 0x00000000
0x21400078 -> 0x00000000
0x2140007c -> 0x00000000
CA>
CA>

k2k_fail_hyp_port1_10g_hyp_port0_ok.txt

Sensor: 15 Res: 54 C Name: Mezz PSU
Sensor: 16 Res: 50 C Name: 1V0 PSU
Sensor: 17 Res: 52 C Name: 0V85 PSU
Sensor: 18 Res: 44 C Name: DSP0 PSU
Sensor: 19 Res: 61 C Name: MEZZA0 PCB
Sensor: 20 Res: 59 C Name: MEZZB0 PCB
Sensor: 21 Res: 55 C Name: MEZZC0 PCB
Sensor: 22 Res: 54 C Name: MEZZA1 PCB
Sensor: 23 Res: 40 C Name: MEZZB1 PCB
Sensor: 24 Res: 42 C Name: MEZZC1 PCB
root@amc-d24a4-rf4:~#
root@amc-d24a4-rf4:~#
root@amc-d24a4-rf4:~#
root@amc-d24a4-rf4:~# dspteststart 1 0x52 1 1
2 0x52 1 1
dspteTest command 0x0052 sent to CORE 1
root@amc-d24a4-rf4:~# dsptestdump 1 1
stdump 2 1
CAD1:Performing Card Init
Waiting for Test Command
HYP_mastertest:DSP:1:
HYP_mastertest:DSP:1: Pass Running Hyperlink at 10G
HYP_mastertest:DSP:1: Version #: 0x02010002; string HYPLNK LLD Revision: 02.01.0
0.02:Mar 27 2015:00:05:09
HYP_mastertest:DSP:1: About to do system setup (PLL, PSC, and DDR)
HYP_mastertest:DSP:1:
HYP_mastertest:DSP:1: Constructed SERDES configs: PLL=0x00000040; RX=0x0046c485;
 TX=0x000d0c05
HYP_mastertest:DSP:1: system setup worked
HYP_mastertest:DSP:1: About to set up HyperLink Peripheral
HYP_mastertest:DSP:1:
HYP_mastertest:DSP:1:Hyperlink Testing Port 0
HYP_mastertest:DSP:1: ======== begin registers before initialization ========
HYP_mastertest:DSP:1:
HYP_mastertest:DSP:1: Revision register contents:
  Raw    = 0x4e902101
HYP_mastertest:D&&
root@amc-d24a4-rf4:~#
root@amc-d24a4-rf4:~# dspteststart 2 0x52 1 1
Test command 0x0052 sent to CORE 2
root@amc-d24a4-rf4:~# dsptestdump 2 1
CAD2:Performing Card Init
Waiting for Test Command
HYP_mastertest:DSP:2:
HYP_mastertest:DSP:2: Pass Running Hyperlink at 10G
HYP_mastertest:DSP:2: Version #: 0x02010002; string HYPLNK LLD Revision: 02.01.0
0.02:Mar 27 2015:00:05:09
HYP_mastertest:DSP:2: About to do system setup (PLL, PSC, and DDR)
HYP_mastertest:DSP:2:
HYP_mastertest:DSP:2: Constructed SERDES configs: PLL=0x00000040; RX=0x0046c485;
 TX=0x000d0c05
HYP_mastertest:DSP:2: system setup worked
HYP_mastertest:DSP:2: About to set up HyperLink Peripheral
HYP_mastertest:DSP:2:
HYP_mastertest:DSP:2:Hyperlink Testing Port 1
HYP_mastertest:DSP:2: ======== begin registers before initialization ========
HYP_mastertest:DSP:2:
HYP_mastertest:DSP:2: Revision register contents:
  Raw    = 0x4e902101
HYP_mastertest:D&&
root@amc-d24a4-rf4:~# dsptestdump 1 1
CAD1:SP:1:
HYP_mastertest:DSP:1: Status register contents:
  Raw        = 0x00003004
HYP_mastertest:DSP:1:
HYP_mastertest:DSP:1: Link status register contents:
  Raw       = 0x00000000
HYP_mastertest:DSP:1:
HYP_mastertest:DSP:1: Control register contents:
  Raw             = 0x00000000
HYP_mastertest:DSP:1:
HYP_mastertest:DSP:1: Control register contents:
  Raw        = 0x00000000
HYP_mastertest:DSP:1: ========= end registers before initialization =======
HYP_mastertest:DSP:1:
HYP_mastertest:DSP:1:
HYP_mastertest:DSP:1: Waiting for other side to come up (       0) - 0x00000000
HYP_mastertest:DSP:1: Waiting for other side to come up (       1) - 0x00000000
HYP_mastertest:DSP:1: Waiting for other side to come up (       2) - 0x00000000
HYP_mastertest:DSP:1: Waiting&&
root@amc-d24a4-rf4:~# dsptestdump 1 1
CAD1: for other side to come up (       3) - 0x00000000
HYP_mastertest:DSP:1: Waiting for other side to come up (       4) - 0x00000000
HYP_mastertest:DSP:1: Waiting for other side to come up (       5) - 0x00000000
HYP_mastertest:DSP:1: Waiting for other side to come up (       6) - 0x00000000
HYP_mastertest:DSP:1: Waiting for other side to come up (       7) - 0x00000000
HYP_mastertest:DSP:1: Waiting for other side to come up (       8) - 0x00000000
HYP_mastertest:DSP:1: Waiting for other side to come up (       9) - 0x00000000
HYP_mastertest:DSP:1: Waiting for other side to come up (      10) - 0x00000000
HYP_mastertest:DSP:1: Waiting for other side to come up (      11) - 0x00000000
HYP_mastertest:DSP:1: Waiting for other side to come up (      12) - 0x000000&&
root@amc-d24a4-rf4:~# dsptestdump 1 1
CAD1:00
HYP_mastertest:DSP:1: Waiting for other side to come up (      13) - 0x00000000
HYP_mastertest:DSP:1: Waiting for other side to come up (      14) - 0x00000000
HYP_mastertest:DSP:1: Waiting for other side to come up (      15) - 0x00000000
HYP_mastertest:DSP:1: Waiting for other side to come up (      16) - 0x00000000
HYP_mastertest:DSP:1: Waiting for other side to come up (      17) - 0x00000000
HYP_mastertest:DSP:1: Waiting for other side to come up (      18) - 0x00000000
HYP_mastertest:DSP:1: Waiting for other side to come up (      19) - 0x00000000
HYP_mastertest:DSP:1: Waiting for other side to come up (      20) - 0x00000000
HYP_mastertest:DSP:1: Waiting for other side to come up (      21) - 0x00000000
HYP_mastertest:DSP:1: Waiting for other side &&
root@amc-d24a4-rf4:~# dsptestdump 1 1
CAD1:to come up (      22) - 0x00000000
HYP_mastertest:DSP:1: Waiting for other side to come up (      23) - 0x00000000
HYP_mastertest:DSP:1: Waiting for other side to come up (      24) - 0x00000000
HYP_mastertest:DSP:1: Waiting for other side to come up (      25) - 0x00000000
HYP_mastertest:DSP:1: Waiting for other side to come up (      26) - 0x00000000
HYP_mastertest:DSP:1: Waiting for other side to come up (      27) - 0x00000000
HYP_mastertest:DSP:1: Checking for Corrected and Non-corrected errors
HYP_mastertest:DSP:1: ====== begin registers after initialization =======
HYP_mastertest:DSP:1:
HYP_mastertest:DSP:1: Status register contents:
  Raw        = 0x04400005
HYP_mastertest:DSP:1:
HYP_mastertest:DSP:1: Link status register contents:
  Raw       = 0xfd&&
root@amc-d24a4-rf4:~# dsptestdump 1 1
CAD1:f0bdf3
HYP_mastertest:DSP:1:
HYP_mastertest:DSP:1: Control register contents:
  Raw             = 0x00006200
HYP_mastertest:DSP:1: ===== end registers after initialization ======
HYP_mastertest:DSP:1: Waiting 5 seconds to check link stability
HYP_mastertest:DSP:1: Checking for Corrected and Non-corrected errors
HYP_mastertest:DSP:1: Checking for Corrected and Non-corrected errors
HYP_mastertest:DSP:1:
HYP_mastertest:DSP:1: Precursors 1
HYP_mastertest:DSP:1:
HYP_mastertest:DSP:1: Checking for Corrected and Non-corrected errors
HYP_mastertest:DSP:1: Link seems stable
HYP_mastertest:DSP:1: About to try to read remote registers
HYP_mastertest:DSP:1: Checking for Corrected and Non-corrected errors
HYP_mastertest:DSP:1: ======== begin REMOTE registers after initi&&
root@amc-d24a4-rf4:~# dsptestdump 1 1
CAD1:alization ======
HYP_mastertest:DSP:1:
HYP_mastertest:DSP:1: Status register contents:
  Raw        = 0x0440000b
HYP_mastertest:DSP:1:
HYP_mastertest:DSP:1: Link status register contents:
  Raw       = 0xfdf0bdfa
HYP_mastertest:DSP:1:
HYP_mastertest:DSP:1: Control register contents:
  Raw             = 0x00006200
HYP_mastertest:DSP:1: ======== end REMOTE registers after initialization ======
HYP_mastertest:DSP:1: Peripheral setup worked
HYP_mastertest:DSP:1: Link Speed is 4 * 10.0 Gbps
hyplnkExampleAddrMap:DSP 1:
&&
root@amc-d24a4-rf4:~# dsptestdump 1 1
Nothing to dump, testlog empty
root@amc-d24a4-rf4:~# dsptestdump 1 1
Nothing to dump, testlog empty
root@amc-d24a4-rf4:~# dsptestdump 1 1
Nothing to dump, testlog empty
root@amc-d24a4-rf4:~# dsptestdump 2 1
CAD2:SP:2:
HYP_mastertest:DSP:2: Status register contents:
  Raw        = 0x00003004
HYP_mastertest:DSP:2:
HYP_mastertest:DSP:2: Link status register contents:
  Raw       = 0x00000000
HYP_mastertest:DSP:2:
HYP_mastertest:DSP:2: Control register contents:
  Raw             = 0x00000000
HYP_mastertest:DSP:2:
HYP_mastertest:DSP:2: Control register contents:
  Raw        = 0x00000000
HYP_mastertest:DSP:2: ========= end registers before initialization =======
HYP_mastertest:DSP:2:
HYP_mastertest:DSP:2:
HYP_mastertest:DSP:2: Waiting for other side to come up (       0) - 0x00000000
HYP_mastertest:DSP:2: Waiting for other side to come up (       1) - 0x00000000
HYP_mastertest:DSP:2: Waiting for other side to come up (       2) - 0x00000000
HYP_mastertest:DSP:2: Waiting&&
root@amc-d24a4-rf4:~# dsptestdump 2 1
CAD2: for other side to come up (       3) - 0x00000000
HYP_mastertest:DSP:2: Waiting for other side to come up (       4) - 0x00000000
HYP_mastertest:DSP:2: Waiting for other side to come up (       5) - 0x00000000
HYP_mastertest:DSP:2: Waiting for other side to come up (       6) - 0x00000000
HYP_mastertest:DSP:2: Waiting for other side to come up (       7) - 0x00000000
HYP_mastertest:DSP:2: Waiting for other side to come up (       8) - 0x00000000
HYP_mastertest:DSP:2: Waiting for other side to come up (       9) - 0x00000000
HYP_mastertest:DSP:2: Waiting for other side to come up (      10) - 0x00000000
HYP_mastertest:DSP:2: Waiting for other side to come up (      11) - 0x00000000
HYP_mastertest:DSP:2: Waiting for other side to come up (      12) - 0x000000&&
root@amc-d24a4-rf4:~# dsptestdump 2 1
CAD2:00
HYP_mastertest:DSP:2: Waiting for other side to come up (      13) - 0x00000000
HYP_mastertest:DSP:2: Waiting for other side to come up (      14) - 0x00000000
HYP_mastertest:DSP:2: Waiting for other side to come up (      15) - 0x00000000
HYP_mastertest:DSP:2: Waiting for other side to come up (      16) - 0x00000000
HYP_mastertest:DSP:2: Waiting for other side to come up (      17) - 0x00000000
HYP_mastertest:DSP:2: Waiting for other side to come up (      18) - 0x00000000
HYP_mastertest:DSP:2: Waiting for other side to come up (      19) - 0x00000000
HYP_mastertest:DSP:2: Waiting for other side to come up (      20) - 0x00000000
HYP_mastertest:DSP:2: Waiting for other side to come up (      21) - 0x00000000
HYP_mastertest:DSP:2: Waiting for other side &&
root@amc-d24a4-rf4:~# dsptestdump 2 1
CAD2:to come up (      22) - 0x00000000
HYP_mastertest:DSP:2: Waiting for other side to come up (      23) - 0x00000000
HYP_mastertest:DSP:2: Waiting for other side to come up (      24) - 0x00000000
HYP_mastertest:DSP:2: Waiting for other side to come up (      25) - 0x00000000
HYP_mastertest:DSP:2: Waiting for other side to come up (      26) - 0x00000000
HYP_mastertest:DSP:2: Waiting for other side to come up (      27) - 0x00000000
HYP_mastertest:DSP:2: Waiting for other side to come up (      28) - 0x00000000
HYP_mastertest:DSP:2: Waiting for other side to come up (      29) - 0x00000000
HYP_mastertest:DSP:2: Waiting for other side to come up (      30) - 0x00000000
HYP_mastertest:DSP:2: Checking for Corrected and Non-corrected errors
HYP_mastertest:DSP:2: P&&
root@amc-d24a4-rf4:~# dsptestdump 2 1
CAD2:ass Local immediately after link up status.rError = 1
HYP_mastertest:DSP:2: Fail Errors Detected, see print messages above
HYP_mastertest:DSP:2: ====== begin registers after initialization =======
HYP_mastertest:DSP:2:
HYP_mastertest:DSP:2: Status register contents:
  Raw        = 0x04400105
HYP_mastertest:DSP:2:
HYP_mastertest:DSP:2: Link status register contents:
  Raw       = 0xfdf0bdf1
HYP_mastertest:DSP:2:
HYP_mastertest:DSP:2: Control register contents:
  Raw             = 0x00006200
HYP_mastertest:DSP:2: ===== end registers after initialization ======
HYP_mastertest:DSP:2: Waiting 5 seconds to check link stability
HYP_mastertest:DSP:2: Checking for Corrected and Non-corrected errors
HYP_mastertest:DSP:2: Pass Local before stability wait status.rError &&
root@amc-d24a4-rf4:~# dsptestdump 2 1
CAD2:= 1
HYP_mastertest:DSP:2: Fail Errors Detected, see print messages above
HYP_mastertest:DSP:2: Checking for Corrected and Non-corrected errors
HYP_mastertest:DSP:2: Pass Local before eq analysis status.rError = 1
HYP_mastertest:DSP:2: Fail Errors Detected, see print messages above
HYP_mastertest:DSP:2:
HYP_mastertest:DSP:2: Precursors 1
HYP_mastertest:DSP:2:
HYP_mastertest:DSP:2: Checking for Corrected and Non-corrected errors
HYP_mastertest:DSP:2: Pass Local after stability wait status.rError = 1
HYP_mastertest:DSP:2: Fail Errors Detected, see print messages above
HYP_mastertest:DSP:2: Link seems stable
HYP_mastertest:DSP:2: About to try to read remote registers
HYP_mastertest:DSP:2: Checking for Corrected and Non-corrected errors
HYP_mastertest:DSP:2: ===&&
root@amc-d24a4-rf4:~# dsptestdump 2 1
CAD2:===== begin REMOTE registers after initialization ======
HYP_mastertest:DSP:2:
HYP_mastertest:DSP:2: Status register contents:
  Raw        = 0x0440000b
HYP_mastertest:DSP:2:
HYP_mastertest:DSP:2: Link status register contents:
  Raw       = 0xfdf0bdf5
HYP_mastertest:DSP:2:
HYP_mastertest:DSP:2: Control register contents:
  Raw             = 0x00006200
HYP_mastertest:DSP:2: ======== end REMOTE registers after initialization ======
HYP_mastertest:DSP:2: Peripheral setup worked
HYP_mastertest:DSP:2: Link Speed is 4 * 10.0 Gbps
hyplnkExampleAddrMap:DSP 2:
&&
root@amc-d24a4-rf4:~# dsptestdump 2 1
Nothing to dump, testlog empty
root@amc-d24a4-rf4:~# dsptestdump 2 1
Nothing to dump, testlog empty
root@amc-d24a4-rf4:~# devmem3 0x21400000 r 128 | hexdump -v -e '"%08_ax: "' -e '
 4/4 "%08x " " |"' -e '16/1 "%_p" "|\n"'
00000000: 4e902101 00006200 04400005 80000000 |.!.N.b....@.....|
00000010: 00000000 00000000 00000000 00000c0a |................|
00000020: 00000000 00000000 00000000 00000c06 |................|
00000030: 00000000 00000000 00000000 11800015 |................|
00000040: 0002b981 07070004 04000400 00000000 |................|
00000050: 00000000 00000000 fdf0bdf3 00200320 |............ . .|
00000060: 00000000 00000000 00000000 00000000 |................|
00000070: ffff0000 00000000 00000000 00000000 |................|
root@amc-d24a4-rf4:~# devmem3 0x21400100 r 128 | hexdump -v -e '"%08_ax: "' -e '
 4/4 "%08x " " |"' -e '16/1 "%_p" "|\n"'
00000000: 4e902101 00006200 04400105 00000002 |.!.N.b....@.....|
00000010: 00000004 00000004 00000000 00000c0a |................|
00000020: 00000000 00000000 00000000 00000c06 |................|
00000030: 00000000 00000000 00000000 12800015 |................|
00000040: 0002b981 07070004 04000400 00000000 |................|
00000050: 00000000 00000000 fdf0bdf1 00200320 |............ . .|
00000060: 00000000 00000000 00000000 00000000 |................|
00000070: ffff0000 00000000 00000000 00000000 |................|
root@amc-d24a4-rf4:~# devmem3 0x0231bfe0 r 80 | hexdump -v -e '"%08_ax: "' -e '
4/4 "%08x " " |"' -e '16/1 "%_p" "|\n"'
00000000: f000f002 f000f002 f000f002 f000f002 |................|
00000010: 00000000 f0000f0f 00000000 000124f8 |.............$..|
00000020: 00820803 00000000 00000000 00000000 |................|
00000030: 00000000 00058282 00000000 00000000 |................|
00000040: 00000000 00000000 a0020000 20414402 |.............DA |
root@amc-d24a4-rf4:~# devmem3 0x0231dfe0 r 80 | hexdump -v -e '"%08_ax: "' -e '
4/4 "%08x " " |"' -e '16/1 "%_p" "|\n"'
00000000: f000f002 f000f002 f000f002 f000f002 |................|
00000010: 00000000 f0000f0f 00000000 000124f8 |.............$..|
00000020: 00800803 00000000 00000000 00000000 |................|
00000030: 00000000 00053838 00000000 00000000 |....88..........|
00000040: 00000000 00000000 a0020000 20414402 |.............DA |
root@amc-d24a4-rf4:~#

0 lding over 8 years ago in reply to skyc0lour

TI__Guru* 95265 points

Due to the lane reversal, the working case:

- K2K port 0/1 link status: 0xfdf0_bdf3/1

- DSP 1: 0xfdf0_bdfa;

-DSP 2: 0xfdf0_bdf5

In your latest dump k2k_fail_hyp_port1_10g_hyp_port0_ok.txt, for port 1:

root@amc-d24a4-rf4:~# devmem3 0x21400100 r 128 | hexdump -v -e '"%08_ax: "' -e '
4/4 "%08x " " |"' -e '16/1 "%_p" "|\n"'
00000000: 4e902101 00006200 04400105 00000002 |.!.N.b....@.....|
00000010: 00000004 00000004 00000000 00000c0a |................|
00000020: 00000000 00000000 00000000 00000c06 |................|
00000030: 00000000 00000000 00000000 12800015 |................|
00000040: 0002b981 07070004 04000400 00000000 |................|
00000050: 00000000 00000000 fdf0bdf1 00200320 |............ . .|

HYP_mastertest:DSP:2: Link status register contents:
Raw = 0xfdf0bdf5
HYP_mastertest:DSP:2:
HYP_mastertest:DSP:2: Control register contents:
Raw = 0x00006200
HYP_mastertest:DSP:2: ======== end REMOTE registers after initialization ======
HYP_mastertest:DSP:2: Peripheral setup worked

Why you think this is an error case?

Regards, Eric

0 skyc0lour over 8 years ago in reply to lding

Intellectual 600 points

Hi Eric,

On similar run before, DSP2 successfully done data transfer but DSP0 PORT1 crashed and in that log it reported link status is fine but correctable and/or non-correctable error occurred.

If you search for ERROR in k2k_fail_hyp_port1_10g_hyp_port0_ok.txt, you will see PORT1 seen an error but not PORT0 of K2K.

I will try to get some more failure case today if i can.

Kind Regards,

Piyush

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Keystone II Hyperlink Rate to 10G