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Is it possible to reprogram UPP Window address (UPID0.ADDR) before the transfer has been started?

Dmitry Gringauz53811
Intellectual 300 points

Hello,

We are using UPP bus on the 6655 DSP to receive large-volume transfers (up to 2 megabytes) from an FPGA. 

UPP receive DMA is always configured, for efficiency of our application.

However, at certain times in our application we need to redirect the transfer to a different buffer *before* the transfer has been initiated by the FPGA.

Is it possible to reconfigure UPP receive DMA after it has already been set up without resetting the whole UPP bus?  That is, is it possible to modify the UPP DMA Window Address after it has been programmed, but before the transfer has been started, without issuing a reset?  And if it is possible, how?

The user guide is very helpful in explaining how the transfers are set up, but, unfortunately, does not contain a lot of information about how to reconfigure and/or modify the settings.

Thank you very much in advance,

Dmitry.

  • 0
    TI__Guru** 116100 points
    Dear Dmitry,
    Please let me do some sanity check and confirm.
    I hope we need uPP peripheral reset to clear all the earlier configured settings.
  • 0
    TI__Guru* 81335 points
    Hi Dmitry,

    I hope, you are working with "Ganz" on this issue. Refer below thread,

    e2e.ti.com/.../476001

    Please confirm. Did the reply from "Mark" helped to debug the issue? Thank you.
  • 0 in reply to Titusrathinaraj Stalin
    Intellectual 300 points
    Hi Titus,

    Please check and let us know.

    We are in a bit of a bind right now. I would prefer to have a way to reconfigure the DMA without resetting the peripheral, but we need a definitive answer. The documentation is not very clear.

    Best Regards,

    Dmitry
  • 0 in reply to Raja
    Intellectual 300 points
    Hi Raja,

    Yes, I do indeed work with Gan on this issue.

    Unfortunately, Mark's reply was incomplete, and lacked examples. We are not looking to schedule a second DMA request. Due to the specifics of our application, we need to modify the one that has already been configured, but that has not been started yet. We would prefer to do it without resetting the whole bus, but the information we have as of now has not been definitive.

    Best Regards,

    Dmitry.
  • 0 in reply to Dmitry Gringauz53811
    TI__Mastermind 42545 points

    Hi Dmitry,

    Changing or redirecting an active DMA is not possible with the architecture of the uPP peripheral. Once the parameters for a DMA are programmed into the device, the pending bit is set high. If the pending bit is set high, the registers for the DMA parameters bits cannot be written without corrupting the state machine operation.  If the channel has been initialized the DMA will begin immediately and the state machine will set the pending bit low to allow the DMA parameters for the next (or pending) DMA to be preloaded. The active DMA must be allowed to finish or the state machine must be cleared using the software reset procedure given in section 2.7.1. Although the DMA provides two independent channels for data transfer, the DMA controller does not have the ability to reset these channel independently. If you issue a software reset, it will reset both the transmit and the receive channels in your system.

    Since the pending DMA parameters are independent of the active DMA parameters, you can redirect the data on a DMA-by-DMA basis. External logic could be used to indicate whether the next data block entering the system is of one type or the second type. The software could check an indicator, such as a GPIO input, to determine the needed type of DMA parameters for the next transfer.  Another alternative would be to tack a header onto the incoming data block and sort the data after it has been written into memory. I don’t see any other alternative to directing the incoming data to multiple destinations.

    Regards,

    Bill

  • 0 in reply to Bill Taboada
    Intellectual 300 points

    Bill,

    Thank you for the definitive answer.

    Best Regards,

    Dmitry.