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Placement of descriptor memory in MSMC SRAM will have performance effects on TCI6638K2K

I would like allocate MSMC SRAM memory for descriptors.
Maybe you could point on some samples in SDK ?
I see several possibility but do not know proper way of doing this.

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  • I am not sure what CPU you want to use, the ARM or the DSP
    In case of DSP, if MSMC memory is available to the DSP, there is not reason why you cannot use insert Region with the MSMC memory address
    In the case of ARM it is a little more involved and has to do with definition of cmem (since the memory should be contiguous and ARM uses MMU)

    In any case, look at the qmss examples in the processor SDK RTOS in the PA example and see how the ARM inserts region

    Ran
  • Ran-

    Apologies for bumping this thread, but could not find another post on this.


    We're using c6678 and need to move PA descriptor queues/handles to MSMC SRAM from DDR3.  We found that we can move everything in pa_mgmt.c and cppi_qmss_mgmt.c except for gHostDesc.  If we place gHostDesc in MSMC packet I/O does not work correctly (no Rx packets received).

    Is there something we're missing ?  An assumption in other code that gHostDesc will be in DDR3 mem space ?

    One note -- we did not move .cppiMemTX and .cppiMemRX, these are still in DDR3 mem (they are too large to move).

    Thanks.

    -Jeff
    Signalogic

  • I may mention this before, or you already know that:

    For 6678, the insert region function must be done in ascending order of the memory address (global memory if the address is in L2). This is due to the way the hardware translates between addresses and indexes of the descriptors. Make sure that you follow this statement.

    Is this your case?  update please

    Best regards

    Ran

  • Hi Ran-

    Thanks for your reply.

    >> For 6678, the insert region function must be done in ascending order of the
    >> memory address

    I can only find one Qmss_insertMemoryRegion() call, in cppi_qmss_mgmt.c:

    memset (gHostDesc, 0, SIZE_HOST_DESC * NUM_HOST_DESC);
    memCfg.descBase             =   (UInt32 *) gHostDesc;
    memCfg.descSize             =   SIZE_HOST_DESC;
    memCfg.descNum              =   NUM_HOST_DESC;
    memCfg.manageDescFlag       =   Qmss_ManageDesc_MANAGE_DESCRIPTOR;
    memCfg.memRegion            =   Qmss_MemRegion_MEMORY_REGION0;
    memCfg.startIndex           =   0;
    result = Qmss_insertMemoryRegion(&memCfg);

    So if this one was DDR3 before, and now it is MSMC, then it should be ok unless there are one or more inserts being done in a TI lib that are not visible in the source.  Could that be the case ?

    Two additional notes:

    1) I have seen a case where Rx packets got started, but stopped after 600 or so for each core (we're using UDP port filtering).  Again, rebuilding with the only change moving gHostDesc back to DDR3 mem allows normal operation.

    2) We did not move cppiMemTX and cppiMemRX, these are still in DDR3 mem.  We could not make enough room in MSMC for these.

    -Jeff

  • Jeff
    My guess is that someone else is over-writing the MSMC memory, otherwise I cannot explain it.

    I remember that the ARM uses some area of the MSMC memory so I assume this is the reason why you see what you see

    My suggestion - Look at the device tree that you use and see if the MSMC memory is defined there. If so, the LINUX may use teh same area

    Does it make sense?

    Regards

    Ran