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no-DDR3, no-IBL, CORE1 - image for flash-spi boot for C6672

Other Parts Discussed in Thread: OMAP-L138

Hi.

I've just designed own board based on FPGA and C6672. My DSP (core0) boots from spi-flash memory successfully. At present all my code is L2/SHAREDRAM based, so I do not use the DDR3. I want to create a system where core0 and core1 realize different programs. My questions:

1. is there a simplest solution for core1 booting without IBL, MAD, DDR3 and without emulator too? (flashing spi memory is based on NIOS2f and works of course)

2. is the MAD is capable to help me in this issue?

3. is there any tools that could merge this two 'output file' together automatically - I have some experience in AISgen_d800k008.exe for OMAP-L138?

Regards,

Pawel

  • Hi,
    I have just read the text "Booting Multiple CorePacs in The Device From I2C" from SPRUGY9C, pp. 3-23. Solution is simple and works.

    //we have to put this "extern void _c_int00(void);" into the code"
    //in other places we must copy L2CORE0 content to L2CORE1 except 256 last bytes....

    pL2CORE0 = (unsigned char *)0x10800000;
    pL2CORE1 = (unsigned char *)0x11800000;

    for(i=0;i<512*1024-256;i++)
    {
    pL2CORE1[i]=pL2CORE0[i];
    }

    void (*x)(void) = _c_int00;
    platform_write(">> _c_int00: 0x%x",x);
    DEVICE_REG32_W(0x1187FFFC, x|0x11000000); //logical OR should be done for global address obtaining for CORE1 L2

    //and wake up the CORE1

    CSL_IPC_genGEMInterrupt( 1, 0 );

    But the issue is not solved. I want to run two programs for DSP independly. So, if anybody has some suggestions...

    Pawel
  • Thank you for the update. You can use DNUM for executing code across multiple core. Thank you.