Hi.
I've just designed own board based on FPGA and C6672. My DSP (core0) boots from spi-flash memory successfully. At present all my code is L2/SHAREDRAM based, so I do not use the DDR3. I want to create a system where core0 and core1 realize different programs. My questions:
1. is there a simplest solution for core1 booting without IBL, MAD, DDR3 and without emulator too? (flashing spi memory is based on NIOS2f and works of course)
2. is the MAD is capable to help me in this issue?
3. is there any tools that could merge this two 'output file' together automatically - I have some experience in AISgen_d800k008.exe for OMAP-L138?
Regards,
Pawel