• State Resolved
  • Locked Locked
  • Replies 2 replies
  • Subscribers 102 subscribers
  • Views 811 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Question About Accessing EMIF-16 Interface & Possible Side Effect of Accessing Emif-16 to the DDR3 Emif

Elric
Expert 1250 points

Hello,

I need a clarification regarding to MSMC access by ARM CorePac (Keystone II - TCI6638k2k).


It is clear from the spruhj6.pdf(MSMC User Guide) that ARM CorePac(4xARM) accesses through a shared access port to the MSMC(ARM CorePac Coherent Slave Port)

My question is :

-       When one of the ARM cores, say ARM Core0 initiates an SRAM/FLASH/FPGA access which is connected to the EMIF16 interface, what happens to another transaction initiated by ARM Core1 to the DDR3 EMIF interface.

-       Will the transaction initated by ARM Core1 stalled untill the transaction initiated to EMIF16 by ARM Core0 completes ?

Regards,

Erman

  • 0
    TI__Guru* 81335 points
    Did you get a chance to look at the EMIF16 User Guide and memory controller user guide for information?

    Thank you.
  • 0 in reply to Raja
    TI__Genius 12805 points
    First I would say that TI LINUX is SMP LINUX so from the user point of view all ARM cores can be looked as a single processor. Regardless, the ARM CorePac has a single access to the MSMC.

    So you are right. If the CorePac tries to simultaneously access two locations there will be some arbitration on the bus. The priority of traffic on the TeraNet bus can be configured, but if I understand correctly your question, in both cases the ARM is the master so the two transfers have the same priority on the bus and the question is which request will be sent on the bus first and how long before the other move is set.

    So the question is how the standard ARM bus that connects the four ARM cores inside the CorePac to the TeraNet bridge deals with two requests at the same time. My guess is that the answer should be in ARM documentations. So look at infocenter.arm.com/.../index.jsp and try to find where ARM describes the access scheme

    Does it make sense?

    Ran