need vcp2 with edma3 config details for 6638 K2k

Hi Anil,

I've attached the example from the aforementioned thread here.

Regards

-Nitin

4010.vcp2example.zip

Hi Nitin,

Thanks a lot,

I am able to download the code and it is building when I am using “SOC_C6657” in the soc.h file,

It is not building when I am trying to use SOC_K2K in the soc.h file. some of the macros are undefined, those macros are not defined in the “cslr_device.h”  for K2K device.

Following macros are shown below, please help on this what equivalent macros i need use for K2K Device to build and run the code. I am waiting for your reply.

identifier "CSL_EDMA3_TPCC2_NUM_DMACH"

identifier "CSL_INTC0_CPU_3_2_TPCCINT0"

identifier "CSL_INTC0_CPU_3_2_TPCCINT0"

identifier "CSL_INTC0_CPU_3_2_TPCCINT1"

identifier "CSL_INTC0_CPU_3_2_TPCCINT2"

identifier "CSL_INTC0_CPU_3_2_TPCCINT3"

identifier "CSL_INTC0_VCP0INT"

identifier "CSL_INTC0_VCP0INT"

identifier "CSL_INTC0_VCP1INT"

identifier "CSL_TPCC_2"

identifier "CSL_TPCC_2"

identifier "CSL_TPCC_2"

identifier "CSL_TPCC_2"

identifier "CSL_TPCC_2"

identifier "CSL_TPCC_2"

identifier "CSL_TPCC_2"

identifier "CSL_TPCC_2"

identifier "CSL_TPCC2_VCP0REVT"

identifier "CSL_TPCC2_VCP0REVT"

identifier "CSL_TPCC2_VCP0REVT"

identifier "CSL_TPCC2_VCP0REVT"

identifier "CSL_TPCC2_VCP0REVT"

identifier "CSL_TPCC2_VCP0REVT"

identifier "CSL_TPCC2_VCP0REVT"

identifier "CSL_TPCC2_VCP0REVT"

identifier "CSL_TPCC2_VCP0REVT"

identifier "CSL_TPCC2_VCP0XEVT"

identifier "CSL_TPCC2_VCP0XEVT"

identifier "CSL_TPCC2_VCP0XEVT"

identifier "CSL_TPCC2_VCP0XEVT"

identifier "CSL_TPCC2_VCP0XEVT"

identifier "CSL_TPCC2_VCP0XEVT"

identifier "CSL_TPCC2_VCP0XEVT"

identifier "CSL_TPCC2_VCP0XEVT"

identifier "CSL_TPCC2_VCP0XEVT"

identifier "CSL_VCP2_A_DATA_REGS"

identifier "CSL_VCP2_A_DATA_REGS"

identifier "CSL_VCP2_A_DATA_REGS"

identifier "CSL_VCP2_A"

FILE.7z

Thanks & regards

Anil Kumar

Hi Anil,

The corresponding K2K csl definitions from pdk_keystone2_3_01_04_07 are given below:

CSL_EDMA3_TPCC2_NUM_DMACH : CSL_EDMACC_2_NUM_DMACH (device\k2k\src\cslr_device.h)
CSL_INTC0_CPU_3_2_TPCCINT0 : CSL_CIC0_EDMACC_2_TC_0_INT (device\k2k\src\csl_device_interrupt.h)
CSL_INTC0_CPU_3_2_TPCCINT1 : CSL_CIC0_EDMACC_2_TC_1_INT (device\k2k\src\csl_device_interrupt.h)
CSL_INTC0_CPU_3_2_TPCCINT2 : CSL_CIC0_EDMACC_2_TC_2_INT (device\k2k\src\csl_device_interrupt.h)
CSL_INTC0_CPU_3_2_TPCCINT3 : CSL_CIC0_EDMACC_2_TC_3_INT (device\k2k\src\csl_device_interrupt.h)
CSL_INTC0_VCP0INT : CSL_CIC0_VCP_0_INT0 (device\k2k\src\csl_device_interrupt.h)
CSL_INTC0_VCP1INT : CSL_CIC0_VCP_1_INT0 (device\k2k\src\csl_device_interrupt.h)
CSL_TPCC_2 : CSL_EDMA3CC_2 (device\k2k\src\cslr_device.h)
CSL_TPCC2_VCP0REVT : CSL_EDMACC_2_VCP_0_REVT0 (device\k2k\src\csl_device_interrupt.h)
CSL_TPCC2_VCP0XEVT : CSL_EDMACC_2_VCP_0_XEVT0 (device\k2k\src\csl_device_interrupt.h)
CSL_VCP2_A_DATA_REGS : CSL_VCP_0_DATA_REGS (device\k2k\src\cslr_device.h)
CSL_VCP2_A : CSL_VCP_0 (device\k2k\src\cslr_device.h)
CSL_PSC_LPSC_VCP2_A : CSL_PSC_LPSC_VCP_0 (device\k2k\src\cslr_device.h)
CSL_PSC_LPSC_VCP2_B : CSL_PSC_LPSC_VCP_1 (device\k2k\src\cslr_device.h)

-Nitin

Hi Nitin,

Thanks a lot for reply,

I am able to get some of the macros from K2K csl definitions pdk_keystone2_3_01_04_07 package, still some of the macros are missing I am not able to build the code,

 Macro “CSL_TPCC_2” which equivalent for K2K is “CSL_EDMA3CC_2“  which you given CSL_TPCC_2: CSL_EDMA3CC_2 (device\k2k\src\cslr_device.h), “CSL_EDMA3CC_2” undefined in the “cslr_device.h” file.

 Macros are shown below, please help on this what equivalent macros i need use for K2K Device to build and run the code. I am waiting for your reply.

 identifier "CSL_CP_INTC_0" is undefined 

identifier "CSL_TPCC_2" is undefined           

identifier "CSL_GEM_INTC0_OUT_8_PLUS_16_MUL_N" is undefined

identifier "CSL_GEM_INTC0_OUT_9_PLUS_16_MUL_N" is undefined

identifier "CSL_INTC0_VCP2INT" is undefined    

identifier "CSL_INTC0_VCP3INT" is undefined    

identifier "CSL_PSC_PD_PD_VCP_BCD" is undefined    

identifier "CSL_TPCC_2" is undefined        

identifier "CSL_TPCC_2" is undefined        

identifier "CSL_TPCC_2" is undefined        

identifier "CSL_TPCC_2" is undefined        

identifier "CSL_TPCC_2" is undefined        

identifier "CSL_TPCC_2" is undefined        

identifier "CSL_TPCC_2" is undefined        

identifier "CSL_TPCC_2" is undefined        

identifier "CSL_VCP2_D" is undefined

File_June_10.7z

Thanks & regards,

Anil Kumar

CSL_EDMA3CC_2 was a typo. It's CSL_EDMACC_2 (line 541).

CSL_CP_INTC_0 -> CSL_CIC_0 (CP_INTC was renamed to CIC in K2K)
CSL_TPCC_2 -> CSL_EDMACC_2 (note the typo listed above)
CSL_GEM_INTC0_OUT_8_PLUS_16_MUL_N -> CSL_C66X_COREPAC_CIC_OUT8_PLUS_16_MUL_N
CSL_GEM_INTC0_OUT_9_PLUS_16_MUL_N -> CSL_C66X_COREPAC_CIC_OUT9_PLUS_16_MUL_N
CSL_INTC0_VCP2INT -> CSL_CIC0_VCP_0_INT2
CSL_INTC0_VCP3INT -> CSL_CIC0_VCP_0_INT3
CSL_PSC_PD_PD_VCP_BCD -> CSL_PSC_PD_VCP_0123 (and/or CSL_PSC_PD_VCP_4567 for VCPs 4, 5, 6, & 7 as there are 8 VCPs on K2K)
CSL_TPCC_2 -> Already defined above
CSL_TPCC_2 -> Already defined above
CSL_TPCC_2 -> Already defined above
CSL_TPCC_2 -> Already defined above
CSL_TPCC_2 -> Already defined above
CSL_TPCC_2 -> Already defined above
CSL_TPCC_2 -> Already defined above
CSL_TPCC_2 -> Already defined above
CSL_VCP2_D -> CSL_VCP_3 (A->0, B->1, C->2, D->3 and 4, 5, 6, 7 for the other 4 VCPs on K2K)

I would again suggest you to use the example code I provided in this thread (rather than using the BER example) as porting the C6670 example to C6638K2K should be easier.

-Nitin

Hi Nitin, 

Thanks a lot for your support,

I am using example code which you provided in this thread, I got all the macros for K2K csl definitions from pdk_keystone2_3_01_04_07 package, able to build the code and running on hardware TCI6638 K2K.

Following observation found while running on hardware, 

1. Enabling VCP2 is done successfully.
2. VCP2_init called and we got handle for VCP2 instance.
3. EDMA3 Initialization done success fully.
4. VCP2_genIc function called and updated input parameters.
5. EDMA Channels setup done for VCP Processing.
6. Enabling the DMA & VCP Interrupts done.
7. We are running “VCP2_start” function, in the CSL_Vcp2EdmaRegs structure values are not updated in the fields all values are seen zero for “VCPIC0” and “VCPIC1”, “VCPIC2”, “VCPIC3”, “VCPIC4”, “VCPIC5”, and in the CSL_Vcp2ConfigRegs structure variable “VCPSTAT0” set to “0x00000018 (Hex) from the VCP2 architecture document it indicates “IFEMP :1 -> Input FIFO buffer is empty”. And “WIC :1-> “Waiting for input configuration words.”

* Please help on this to resolve the issue might be having some configuration issue. I am waiting for your reply.

 Thanks & regards,

Anil Kumar

Anil,

I have ported the C6670 example provided earlier to 6638 K2K as attached. It uses 4 of the 8 VCP2 instances available on K2K. The build instructions are available in the included ReadMe.txt.

I have tested it on single core (core-0) as well as simultaneously on 4 cores  and it passed. When run on Core-0, it produces the following output:

[Core0][doVCP2Test]: Enabling VCP2-0

[Core0][doVCP2Test]: Enabling VCP2-1

[Core0][doVCP2Test]: Enabling VCP2-2

[Core0][doVCP2Test]: Enabling VCP2-3

Test Result : Passed

-Nitin

vcp2example_K2K.zip

Anil,

Here's what you need to do to use VCPs 4 to 7:

1. If you look at the interrupt mapping defined in 6638_K2K data sheet and correspondingly the k2k csl_device_interrupt.h, you'll see that the transmit and receive events for VCP IDs 4-7 are mapped to EDMACC_3 while we are using EDMACC_2 for VCPs 0-3. However, the good news is that VCPs 0-3 are also mapped to EDMACC_3 as shown in the relevant section below from cslr_device_interrupt.h. (I have pasted the definitions for both EDMACC2 and 3 to show the difference pointed here. The currently used ones are in RED and striken out to emphasize that you need to replace these). So you need to move the EDMA setup code to use EDMACC_3.

cslr_device_interrupt.h
------------------------
#define CSL_EDMACC_2_VCP_0_REVT0 (0x00000033)
#define CSL_EDMACC_2_VCP_0_XEVT0 (0x00000034)
#define CSL_EDMACC_2_VCP_0_REVT1 (0x00000035)
#define CSL_EDMACC_2_VCP_0_XEVT1 (0x00000036)
#define CSL_EDMACC_2_VCP_0_REVT2 (0x00000037)
#define CSL_EDMACC_2_VCP_0_XEVT2 (0x00000038)
#define CSL_EDMACC_2_VCP_0_REVT3 (0x00000039)
#define CSL_EDMACC_2_VCP_0_XEVT3 (0x0000003A)
..............
..............
#define CSL_EDMACC_3_VCP_0_REVT0 (0x00000028)
#define CSL_EDMACC_3_VCP_0_XEVT0 (0x00000029)
#define CSL_EDMACC_3_VCP_0_REVT1 (0x0000002A)
#define CSL_EDMACC_3_VCP_0_XEVT1 (0x0000002B)
#define CSL_EDMACC_3_VCP_0_REVT2 (0x0000002C)
#define CSL_EDMACC_3_VCP_0_XEVT2 (0x0000002D)
#define CSL_EDMACC_3_VCP_0_REVT3 (0x0000002E)
#define CSL_EDMACC_3_VCP_0_XEVT3 (0x0000002F)
#define CSL_EDMACC_3_VCP_1_REVT0 (0x00000030)
#define CSL_EDMACC_3_VCP_1_XEVT0 (0x00000031)
#define CSL_EDMACC_3_VCP_1_REVT1 (0x00000032)
#define CSL_EDMACC_3_VCP_1_XEVT1 (0x00000033)
#define CSL_EDMACC_3_VCP_1_REVT2 (0x00000034)
#define CSL_EDMACC_3_VCP_1_XEVT2 (0x00000035)
#define CSL_EDMACC_3_VCP_1_REVT3 (0x00000036)
#define CSL_EDMACC_3_VCP_1_XEVT3 (0x00000037)

2. Now, if you look at cslr_device_interrupt.h some more, you'll find that the completion events for EDMACC_3 are mapped to CIC_1 (we are currently using CIC_0). So change the interrupt setup code in vcp2_interrupt.h to CIC1. I have pasted the relevant definitions below. (You can find any other required definitions by searching cslr_device_interrupt.h and cslr_device.h).

#define CSL_CIC1_EDMACC_3_TC_0_INT (0x000000E1)
#define CSL_CIC1_EDMACC_3_TC_1_INT (0x000000E2)
#define CSL_CIC1_EDMACC_3_TC_2_INT (0x000000E3)
#define CSL_CIC1_EDMACC_3_TC_3_INT (0x000000E4)
#define CSL_CIC1_EDMACC_3_TC_4_INT (0x000000E5)
#define CSL_CIC1_EDMACC_3_TC_5_INT (0x000000E6)
#define CSL_CIC1_EDMACC_3_TC_6_INT (0x000000E7)
#define CSL_CIC1_EDMACC_3_TC_7_INT (0x000000E8)

3. Corresponding to the changes mentioned in item#2, you'll need to use the C66x_COREPAC events for event outputs coming from CIC1. You'll need to change the code listed below (vcp2_interrupt.h).

// Map GEM input interrupt used for EDMA completion to vectId1
hIntcEdma = CSL_intcOpen(&intcObjEdma,
CSL_C66X_COREPAC_CIC_OUT8_PLUS_16_MUL_N, <======= Change these to use CIC_1 outputs
&vectId1,
NULL);

// Map GEM input interrupt used for VCP error to vectId2 
hIntcVcp = CSL_intcOpen(&intcObjVcp,
CSL_C66X_COREPAC_CIC_OUT9_PLUS_16_MUL_N, <=======
&vectId2,
NULL);

hCpintc = CSL_CPINTC_open(CSL_CIC_0); <====== Change this to use CSL_CIC_1

4. Change the interrupt mappings to use the EDMA completion events listed in item#1 accordingly. Also change the VCP events to use the corresponding events on CIC1. Basically modify all the mapping code given below. 

// Map EDMA completion and VCP error system interrupts to proper output interrupts (channels) and enable
if (coreNum == 0) {
CSL_CPINTC_mapSystemIntrToChannel (hCpintc, CSL_CIC0_EDMACC_2_TC_0_INT, (16 * coreNum) + 8);
CSL_CPINTC_mapSystemIntrToChannel (hCpintc, CSL_CIC0_VCP_0_INT0, (16 * coreNum) + 9);
CSL_CPINTC_enableSysInterrupt (hCpintc, CSL_CIC0_EDMACC_2_TC_0_INT);
CSL_CPINTC_enableSysInterrupt (hCpintc, CSL_CIC0_VCP_0_INT0);
} else if (coreNum == 1) {
CSL_CPINTC_mapSystemIntrToChannel (hCpintc, CSL_CIC0_EDMACC_2_TC_1_INT, (16 * coreNum) + 8);
CSL_CPINTC_mapSystemIntrToChannel (hCpintc, CSL_CIC0_VCP_0_INT1, (16 * coreNum) + 9);
CSL_CPINTC_enableSysInterrupt (hCpintc, CSL_CIC0_EDMACC_2_TC_1_INT);
CSL_CPINTC_enableSysInterrupt (hCpintc, CSL_CIC0_VCP_0_INT1);
} else if (coreNum == 2) {
CSL_CPINTC_mapSystemIntrToChannel (hCpintc, CSL_CIC0_EDMACC_2_TC_2_INT, (16 * coreNum) + 8);
CSL_CPINTC_mapSystemIntrToChannel (hCpintc, CSL_CIC0_VCP_0_INT2, (16 * coreNum) + 9);
CSL_CPINTC_enableSysInterrupt (hCpintc, CSL_CIC0_EDMACC_2_TC_2_INT);
CSL_CPINTC_enableSysInterrupt (hCpintc, CSL_CIC0_VCP_0_INT2);
} else if (coreNum == 3) {
CSL_CPINTC_mapSystemIntrToChannel (hCpintc, CSL_CIC0_EDMACC_2_TC_3_INT, (16 * coreNum) + 8);
CSL_CPINTC_mapSystemIntrToChannel (hCpintc, CSL_CIC0_VCP_0_INT3, (16 * coreNum) + 9);
CSL_CPINTC_enableSysInterrupt (hCpintc, CSL_CIC0_EDMACC_2_TC_3_INT);
CSL_CPINTC_enableSysInterrupt (hCpintc, CSL_CIC0_VCP_0_INT3);
} else if (coreNum == 4) {
CSL_CPINTC_mapSystemIntrToChannel (hCpintc, CSL_CIC0_EDMACC_2_TC_4_INT, (16 * coreNum) + 8);
CSL_CPINTC_mapSystemIntrToChannel (hCpintc, CSL_CIC0_VCP_1_INT0, (16 * coreNum) + 9);
CSL_CPINTC_enableSysInterrupt (hCpintc, CSL_CIC0_EDMACC_2_TC_4_INT);
CSL_CPINTC_enableSysInterrupt (hCpintc, CSL_CIC0_VCP_1_INT0);
} else if (coreNum == 5) {
CSL_CPINTC_mapSystemIntrToChannel (hCpintc, CSL_CIC0_EDMACC_2_TC_5_INT, (16 * coreNum) + 8);
CSL_CPINTC_mapSystemIntrToChannel (hCpintc, CSL_CIC0_VCP_1_INT1, (16 * coreNum) + 9);
CSL_CPINTC_enableSysInterrupt (hCpintc, CSL_CIC0_EDMACC_2_TC_5_INT);
CSL_CPINTC_enableSysInterrupt (hCpintc, CSL_CIC0_VCP_1_INT1);
} else if (coreNum == 6) {
CSL_CPINTC_mapSystemIntrToChannel (hCpintc, CSL_CIC0_EDMACC_2_TC_6_INT, (16 * coreNum) + 8);
CSL_CPINTC_mapSystemIntrToChannel (hCpintc, CSL_CIC0_VCP_1_INT2, (16 * coreNum) + 9);
CSL_CPINTC_enableSysInterrupt (hCpintc, CSL_CIC0_EDMACC_2_TC_6_INT);
CSL_CPINTC_enableSysInterrupt (hCpintc, CSL_CIC0_VCP_1_INT2);
} else {
CSL_CPINTC_mapSystemIntrToChannel (hCpintc, CSL_CIC0_EDMACC_2_TC_7_INT, (16 * coreNum) + 8);
CSL_CPINTC_mapSystemIntrToChannel (hCpintc, CSL_CIC0_VCP_1_INT3, (16 * coreNum) + 9);
CSL_CPINTC_enableSysInterrupt (hCpintc, CSL_CIC0_EDMACC_2_TC_7_INT);
CSL_CPINTC_enableSysInterrupt (hCpintc, CSL_CIC0_VCP_1_INT3);
}

5. Finally, the CFG address macros defined in vcp_testInit.h will not work for VCPs 4 to 7 as shown below from cslr_device.h. So you need to define new macros for VCPs 4 to 7 and use them accordingly in the EDMA setup. 

cslr_device.h
-------------
#define CSL_VCP_0_CFG_REGS (0x021D0000)
#define CSL_VCP_1_CFG_REGS (0x021D4000)
#define CSL_VCP_2_CFG_REGS (0x021D8000)
#define CSL_VCP_3_CFG_REGS (0x021DC000)
....
....
#define CSL_VCP_4_CFG_REGS (0x02340000)
#define CSL_VCP_5_CFG_REGS (0x02344000)
#define CSL_VCP_6_CFG_REGS (0x02348000)
#define CSL_VCP_7_CFG_REGS (0x0234C000)

Basically, you'll need to define new macros for VCPs 4-7 here and use them accordingly during EDMA setup in cp2_edma.c. 

// Select instance of VCP2 (0-3)

#define VCP2_CONTROL_BASE(vcp2Inst) (CSL_VCP_0_CFG_REGS + (vcp2Inst * 0x4000))
#define VCP2_DATA_BASE(vcp2Inst) (CSL_VCP_0_DATA_REGS + (vcp2Inst * 0x100000))
//#define hVcp2 hVcp2_0

#define VCP2_ICMEM_ADDR(vcp2Inst) (VCP2_DATA_BASE(vcp2Inst) + 0x000000u)
#define VCP2_OPMEM_ADDR(vcp2Inst) (VCP2_DATA_BASE(vcp2Inst) + 0x000048u)
#define VCP2_BMMEM_ADDR(vcp2Inst) (VCP2_DATA_BASE(vcp2Inst) + 0x000080u)
#define VCP2_HDMEM_ADDR(vcp2Inst) (VCP2_DATA_BASE(vcp2Inst) + 0x0000C0u)
#define VCP2_END_ADDR(vcp2Inst) (VCP2_CONTROL_BASE(vcp2Inst) + 0x000020)
#define VCP2_EXE_ADDR(vcp2Inst) (VCP2_CONTROL_BASE(vcp2Inst) + 0x000018)
#define VCP2_STATUS0_ADDR(vcp2Inst) (VCP2_CONTROL_BASE(vcp2Inst) + 0x000040)
#define VCP2_STATUS1_ADDR(vcp2Inst) (VCP2_CONTROL_BASE(vcp2Inst) + 0x000044)
#define VCP2_ERROR_ADDR(vcp2Inst) (VCP2_CONTROL_BASE(vcp2Inst) + 0x000050)
#define VCP2_EMU_ADDR(vcp2Inst) (VCP2_CONTROL_BASE(vcp2Inst) + 0x000060)

The current DATA address macros should work fine since the DATA addresses for VCPs 0-7 are contiguous as shown below (from cslr_device.h).

#define CSL_VCP_0_DATA_REGS (0x22A00000)
#define CSL_VCP_1_DATA_REGS (0x22B00000)
#define CSL_VCP_2_DATA_REGS (0x22C00000)
#define CSL_VCP_3_DATA_REGS (0x22D00000)
#define CSL_VCP_4_DATA_REGS (0x22E00000)
#define CSL_VCP_5_DATA_REGS (0x22F00000)
#define CSL_VCP_6_DATA_REGS (0x23000000)
#define CSL_VCP_7_DATA_REGS (0x23100000)

-Nitin

Anil,

I would strongly recommend you to understand the Kepler-2 interrupt architecture defined in section 6.3 of the TCI6638K2K datasheet. Figure 6-5 (Interrupt Topology) shows that CIC-0 events are routed to C66x cores 0 to 4 and CIC-1 events are mapped to C66x cores 4-7. This is also mentioned in the footnote 1 to table 6-22 (System Event Mapping - C66x CorePac primary interrupts):

"1 For C66x CorePac[0-3], this generic primary interrupt comes from CIC0 and for C66x CorePac[4-7], this generic primary interrupt comes from CIC1."

This means that the general purpose interrupt outputs listed in table 6-22 (e.g. CIC_OUT8_PLUS_16_MUL_N, CIC_OUT9_PLUS_16_MUL_N etc) are provided to cores 0-3 by CIC0 while the same outputs for cores 4-7 are provided by CIC1.

So you need to use CIC1 (which in turn means EDMACC_3 as it's event outputs are mapped to CIC1) for VCPs 4-7 and CIC0 (i.e. the existing setup for the first 4 VCPs) for VCPs 0-3.

1. You need to instantiate CIC1 also in Setup_Interrupt() i.e.

If(DNUM <=3)
{
//----------------------------------------------------------
// Setup CP_INTC0
//----------------------------------------------------------
// Open a handle to CP_INTC instance 0
hCpintc = CSL_CPINTC_open(CSL_CIC_0);
if (hCpintc_0 == 0)
{
printf ("Error: Unable to open CPINT instance 0\n");
return;
}
}
else
{
//----------------------------------------------------------
// Setup CP_INTC1
//----------------------------------------------------------

// Open a handle to CP_INTC instance 1
hCpintc_1 = CSL_CPINTC_open(CSL_CIC_1);
if (hCpintc_1 == 0)
{
printf ("Error: Unable to open CPINT instance 1\n");
return;
}
}

2. Enable host interrupts for CIC1 (again, conditionally for cores 4-7):

// Enable output (host) interrupts to GEM
CSL_CPINTC_enableHostInterrupt (hCpintc_1, (16 * coreNum) + 8);
CSL_CPINTC_enableHostInterrupt (hCpintc_1, (16 * coreNum) + 9);

// Enable global host interrupt enable
CSL_CPINTC_enableAllHostInterrupt(hCpintc_1);


3. Corresponding to this, extend the EDMA interrupt mapping in the same function. Keep the setup for VCPs 0-3 as-is but use the definitions for EDMACC_3 provided earlier, for VCPs 4-7.

4. You'll need to add conditional code or a parameter (for EDMACC 2 or 3) to the EDMA setup function setupVcpMultEdma3 to use EDMACC_3 for cores 4-7.

5. The code for mapping CIC interrupts to C66x core interrupt vectors should work as-is since the corresponding events (CSL_C66X_COREPAC_CIC_OUT8_PLUS_16_MUL_N and CSL_C66X_COREPAC_CIC_OUT9_PLUS_16_MUL_N) for cores 4-7 are provided by CIC1 automatically.

-Nitin

Hi Anil,

As Raja suggested, there are plenty of resources within TI E2E and in TI documentation itself. I would start with understanding the SYSBIOS programming model (SYS BIOS users guide). It's logical that you have to separate the interrupt setup and handling outside the task.

Interrupts need to be setup before calling BIOS_start. As far as handling is concerned, interrupts are never serviced inside a task as they occur asynchronously and are serviced in the corresponding ISR. The task usually is a while(1) loop waiting on a semaphore which is posted by the ISR and you handle the task specific runtime functions (e.g. sending the input packets to the VCP in this case) in the task which need to happen every time the task is woken up by the ISR. You simply cannot move your whole program inside the task function.

Just like any other interrupt driven system, a Hardware Interrupt (HWI) causes the program flow to jump to the ISR asynchronously. I would recommend you to go through some of the examples provided with the Keystone PDK and read the SYSBIOS users guide to understand these concepts.

Regards

-Nitin

need vcp2 with edma3 config details for 6638 K2k

Anil,

We don't have plans to port the example to use 2 VCPs per core. But the behavior you indicated seems logical for the current example as all the EDMA and interrupt configuration and ISR functions operate a core basis.

1. EDMA TCC interrupts (and VCP error interrupts): Each core registers and gets the EDMA TC events meant for itself. You cannot get an interrupt means for one core on the other. An alternative would be to not use completion events and wait for a given time after submitting the input configuration and soft decisions and poll the events currently being handled in the EDMA_ISR, in software synchronously instead of using the ISR. That way you can monitor any/all events on any given core.   

2. EDMA Region Access setup: The current EDMA setup function (edma3ModuleInit, setupVcpTputEdma3 and edma3MultChnlEnable) restrict each core to be able to access only the DMA regions allowed to it. You'll need to understand and modify these function to remove these restrictions as per your application needs and provide access to multiple DMA regions to each core to allow it to program and use the EDMA regions for other VCPs.

-Nitin 

Anil,

I'm out of office this week and shall be able to look into your query when I'm back next week.

Thanks

-Nitin

Anil,

I'm not sure I understand your requirement so you'll need to clarify it in some detail. You should be able to refer to the PDK exmaples to understand interrupt setup on the TCI6638 device.

-Nitin

Anil,

As mentioned in my previous post, your requirement is not clear to me. What do you mean by Interrupt setup inside the task? As already indicated in an earlier post, interrupt functions are not invoked inside a task as they are called asynchronously when the specified event occurs, and the interrupt functions posts a semaphore on which the task function pends (usually). This has already been discussed and there are examples in the PDK which can be used to understand this along with understanding the basics of tasks and interrupts as given in the SYSBIOS user's guide.

-Nitin