infrastructure_multicoremode.c explanation for QMSS

Ranjit Kumar19

In the function void hiPrioInterruptHandler (uint32_t eventId)

/* Process ISR. Read accumulator list */
temp = l2_global_address ((uint32_t) hiPrioList);
temp &= 0xf0ffffff;
buf = (uint32_t *) temp;
count = buf[0];

Here i am unable to understand why temp is & with 0xf0ffffff;

This anding will force all of the cores to read from L2 SRAM of CorePac0 which shouldn't be the case.

Data should be DMAed to respective L2SRAM of each core(so no anding) and then they should be able to process the data from there.

I tried removing the "&" operation but then packet received becomes 0 instead of 8.

Please help

over 7 years ago

0 Raja over 7 years ago

TI__Guru* 81335 points

I will ask our experts to comment here. Thank you.

0 ran35366 over 7 years ago

TI__Genius 12805 points

You are right. The and with 0xf0ff ffff strip down the core number and set it to 0.

I am not sure why it was done like this. It might be a bug, or there is a reason why it was done like this. To analyze this case please tell me what release you are looking and what file. Is it part of example or a generic function?

Thanks

Ran

0 Ranjit Kumar19 over 7 years ago in reply to ran35366

Intellectual 280 points

Thanks for your reply Ran. This is an Example Code

E:\ti\pdk_k2l_4_0_1\packages\ti\drv\qmss\example\InfraDmaMC\src\infrastructure_multicoremode.c

Regards

Ranjit

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infrastructure_multicoremode.c explanation for QMSS