K2E DDR3 Debug GEL failed to read memory for EMIF Report

Larry McCrigler

I am debugging DDR3 on a custom K2E design based on the EVMK2E. I'm using the evmk2e.gel to initialize things and the Keysteone2_DDR_Debug_v1_4.gel to gather reports.

All works fine on my EVMK2E (EVM ver 1.0.2.2) but on my custom design I can get the PLL report and the PHY report, but not the EMIF report. I have tried several times and re-booted everything. The behavior is consistent.

I get the following error:

C66xx_0: Trouble Reading Memory Block at 0x21010008 on Page 0 of Length 0x4: (Error -1202 @ 0x21010008) Device core is hung. The debugger will attempt to force the device to a ready state to recover debug control. Your application's state will be corrupt. You should have limited access to memory and registers, but you may need to reset the device to debug further. (Emulation package 6.0.228.0)
Complete_Report_DDR3A_EMIF_Configuration() cannot be evaluated.
Target failed to read 0x21010008
at (*((int *) (0x21010000+0x00000008))&0xE0000000) [Keystone2_DDR_Debug_v1_4.gel]
at printDDR3A_EMIF_SDCFG() [Keystone2_DDR_Debug_v1_4.gel:434]
at printDDR3A_EMIF() [Keystone2_DDR_Debug_v1_4.gel:2228]
at Complete_Report_DDR3A_EMIF_Configuration()

I did review the PLL report and everything looks good. I need to make changes to the configuration of the PHY - but I don't think that should cause the problem with the EMIF report.

Thanks in advance for any ideas,

Larry McCrigler

over 7 years ago

0 Titusrathinaraj Stalin over 7 years ago

TI__Guru** 116100 points

Dear Larry McCrigler,
Please make sure that your DDR timing configuration is proper.
Try to reduce the DDR3 clock speed and see if that helps.
Refer to the following TI wiki page.
processors.wiki.ti.com/.../K2Ex_Hardware_Design_Guide

0 Senthilkumar Srinivasan over 7 years ago

TI__Mastermind 43660 points

Larry,

It should be a configuration issue. As Titus mentioned, please ensure the timing configuration and check.

Regards,
Senthil

0 Larry McCrigler over 7 years ago in reply to Senthilkumar Srinivasan

Prodigy 210 points

Senthil,

Agreed - it's likely a configuration issue. I am reviewing the configuration details today and making changes where necessary. I expect to retest today and see if that corrects the issue. I'll verify this thread as soon as I retest.

Thanks again for the guidance,

Larry

0 Rahul Prabhu over 7 years ago

TI__Guru** 114410 points

Larry,

Are you configuring MPAX registers before reading DDR Config registers. K2E has a 36 bit Addressable space and Keystone DDR configuration registers are physically located above 32-bit addresses and are mapped via the MPAX configuration to the address 0x21000000. the function initXMC in the GEL make these registers visible in the 32 bit address space :

/*--------------------------------------------------------------*/
/* xmc_setup() */
/* XMC MPAX register setting to access DDR3 config space */
/*--------------------------------------------------------------*/

#define XMC_BASE_ADDR (0x08000000)
#define XMPAX2_L (*(int*)(XMC_BASE_ADDR + 0x00000010))
#define XMPAX2_H (*(int*)(XMC_BASE_ADDR + 0x00000014))

xmc_setup()
{
/* mapping for ddr emif registers XMPAX*2 */

XMPAX2_L = 0x121010FF; /* replacement addr + perm */
XMPAX2_H = 0x2101000B; /* base addr + seg size (64KB)*/ //"1B"-->"B" by xj
GEL_TextOut("XMC setup complete.\n");
}

However even if you didn`t have this setup, you should have read all 0x00000000 so I am not sure if this is the root cause of your error.

Regards,
Rahul

0 Larry McCrigler over 7 years ago in reply to Rahul Prabhu

Prodigy 210 points

Rahul,

I will look into this. At the moment the processor comes up in bootmode 0x00000007 (ready for UART) so I get "no initialization performed" message from the GEL.
I then use GlobalDefaultSetup script to configure everything (evmk2e.gel) I've modified this .gel to set the values to what I expect. However, now when I get to EMIF configuration part of the gel I have trouble reading block error.

I am considering changing the bootmode so I don't have to manually run GlobalDefaultSetup
I will look into your suggestion.
I am relying on GlobalDefaultSetup to get everything configured.

Larry

0 Larry McCrigler over 7 years ago in reply to Rahul Prabhu

Prodigy 210 points

Rahul,

initXMC corrected the issue and GlobalDefaultSetup completed without error.

Thank you! I will proceed with DDR3 debug and verification.
Larry McCrigler

0 Larry McCrigler over 7 years ago in reply to Larry McCrigler

Prodigy 210 points

Rahul,
I am proceeding with DDR3 debug and verification using DDR3 Debug GEL. I have logs from DDR3 Debug GEL, which look good to me so far. I have two questions.

In leveling report - I see PGSR0 [11] to PGSR0 [0] = NOT SET I'm not sure why, but I'm looking into it. Suggestions?

In DDR_Write_Read_Test (it fails) I get the following error (below) - I'm wondering if this is another memory map thing?

C66xx_0: GEL Output: Memory Test Write Core: 0, Mem Start: 0x0x80000000, Mem Size: 0x0x00000100, value: 0x0xAAAAAAAA ...
C66xx_0: GEL Output: Memory Test Read Core: 0, Mem Start: 0x0x80000000, Mem Size: 0x0x00000100 ...
C66xx_0: Trouble Reading Memory Block at 0x80000000 on Page 0 of Length 0x4: (Error -1202 @ 0x80000000) Device core is hung. The debugger will attempt to force the device to a ready state to recover debug control. Your application's state will be corrupt. You should have limited access to memory and registers, but you may need to reset the device to debug further. (Emulation package 6.0.407.3)
ddr3A_write_read_test() cannot be evaluated.
Target failed to read 0x80000000
at read_data=*((unsigned int *) mem_location) [USL_evmk2e.gel:2759]
at ddr3A_write_read_test()C66xx_0: 2 other operation(s) were automatically canceled as a result
C66xx_0: Trouble Reading Register ControlRegisters_CSR: (Error -1202 @ 0x41) Device core is hung. The debugger will attempt to force the device to a ready state to recover debug control. Your application's state will be corrupt. You should have limited access to memory and registers, but you may need to reset the device to debug further. (Emulation package 6.0.407.3)
C66xx_0: 8 other operation(s) were automatically canceled as a result

My next step is reviewing the Debug GEL reports and working through the DDR3 debug worksheet.

Thanks,
Larry

0 Rahul Prabhu over 7 years ago in reply to Larry McCrigler

TI__Guru** 114410 points

Larry,

No, this is unlikely to be memory mapping issue. I think this is most likely DDR configuration or leveling issue. I have pinged a DDR expert to look into the observation that you have shared. He will get back to you soon.

Regards,
Rahul

0 Senthilkumar Srinivasan over 7 years ago in reply to Larry McCrigler

TI__Mastermind 43660 points

Larry,

Are you able to write any value directly on the DDR memory location in CCS ?

Are you seeing errors on any particular byte when you read back ? Please share the memory contents when you do DDR_Write_Read_Test.

Regards,
Senthil

0 Larry McCrigler over 7 years ago in reply to Senthilkumar Srinivasan

Prodigy 210 points

Senthil, << sorry I was away from the office for a few days. I'm back now. >>

I cannot read anything from DDR3. Here is the results of the DDR_Write_Read_Test which I did after Global Default Setup.

C66xx_0: GEL Output: Global Default Setup... Done.
C66xx_0: GEL Output: Memory Test Write Core: 0, Mem Start: 0x0x80000000, Mem Size: 0x0x00000100, value: 0x0xAAAAAAAA ...
C66xx_0: GEL Output: Memory Test Read Core: 0, Mem Start: 0x0x80000000, Mem Size: 0x0x00000100 ...
C66xx_0: Trouble Reading Memory Block at 0x80000000 on Page 0 of Length 0x4: (Error -1202 @ 0x80000000) Device core is hung. The debugger will attempt to force the device to a ready state to recover debug control. Your application's state will be corrupt. You should have limited access to memory and registers, but you may need to reset the device to debug further. (Emulation package 6.0.407.3)
C66xx_0: Trouble Reading Memory Block at 0x80000000 on Page 0 of Length 0x4: (Error -1202 @ 0x80000000) Device core is hung. The debugger will attempt to force the device to a ready state to recover debug control. Your application's state will be corrupt. You should have limited access to memory and registers, but you may need to reset the device to debug further. (Emulation package 6.0.407.3)
ddr3A_write_read_test() cannot be evaluated.
Target failed to read 0x80000000
at read_data=*((unsigned int *) mem_location) [USL_evmk2e.gel:2759]
at ddr3A_write_read_test()C66xx_0: 2 other operation(s) were automatically canceled as a result
C66xx_0: Trouble Reading Register ControlRegisters_CSR: (Error -1202 @ 0x41) Device core is hung. The debugger will attempt to force the device to a ready state to recover debug control. Your application's state will be corrupt. You should have limited access to memory and registers, but you may need to reset the device to debug further. (Emulation package 6.0.407.3)
C66xx_0: 8 other operation(s) were automatically canceled as a result

At the moment I am filling in the DDR3 Debug worksheet and reviewing the Debug Reports (PHY,PLL,EMIF) I am also seeing errors in the leveling report -

C66xx_0: GEL Output: ****************************************************************************************************************
C66xx_0: GEL Output: ***************** DDR3A Leveling Errors *********************
C66xx_0: GEL Output: PGSR0[27]: WEERR has ** No Error **
C66xx_0: GEL Output: PGSR0[26]: REERR has ** No Error **
C66xx_0: GEL Output: PGSR0[25]: WDERR has ** No Error **
C66xx_0: GEL Output: PGSR0[24]: RDERR has ** Error **
C66xx_0: GEL Output: PGSR0[23]: WLAERR has ** Error **
C66xx_0: GEL Output: PGSR0[22]: QSGERR has ** Error **
C66xx_0: GEL Output: PGSR0[21]: WLERR has ** No Error **
C66xx_0: GEL Output: PGSR0[20]: ZCERR has ** No Error **

C66xx_0: GEL Output: PGSR0[11]: WEDONE is ** Not Set **
C66xx_0: GEL Output: PGSR0[10]: REDONE is ** Not Set **
C66xx_0: GEL Output: PGSR0[9]:  WDDONE is ** Not Set **
C66xx_0: GEL Output: PGSR0[8]:  RDDONE is ** Set **
C66xx_0: GEL Output: PGSR0[7]:  WLADONE is ** Set **
C66xx_0: GEL Output: PGSR0[6]:  QSGDONE is ** Set **
C66xx_0: GEL Output: PGSR0[5]:  WLDONE is ** Set **
C66xx_0: GEL Output: PGSR0[4]:  DIDONE is ** Set **
C66xx_0: GEL Output: PGSR0[3]:  ZCDONE is ** Set **
C66xx_0: GEL Output: PGSR0[2]:  DCDONE is ** Set **
C66xx_0: GEL Output: PGSR0[1]:  PLDONE is ** Set **
C66xx_0: GEL Output: PGSR0[0]:  IDONE is ** Set **

C66xx_0: GEL Output: ********************************************************
C66xx_0: GEL Output: Leveling Errors by Byte Lane:

C66xx_0: GEL Output: Byte Lane 0:
C66xx_0: GEL Output: DX0GSR2[6]:   WEERR has   ** No Error **
C66xx_0: GEL Output: DX0GSR2[4]:   REERR has   ** No Error **
C66xx_0: GEL Output: DX0GSR2[2]:   WDERR has   ** No Error **
C66xx_0: GEL Output: DX0GSR2[0]:   RDERR has   ** Error **
C66xx_0: GEL Output: DX0GSR0[25]:   QSGERR on Rank1 has ** No Error **
C66xx_0: GEL Output: DX0GSR0[24]:   QSGERR on Rank0 has ** Error **
C66xx_0: GEL Output: DX0GSR0[6]:    WLERR has   ** No Error **
C66xx_0: GEL Output: Byte Lane 1:
C66xx_0: GEL Output: DX1GSR2[6]:   WEERR has   ** No Error **
C66xx_0: GEL Output: DX1GSR2[4]:   REERR has   ** No Error **
C66xx_0: GEL Output: DX1GSR2[2]:   WDERR has   ** No Error **
C66xx_0: GEL Output: DX1GSR2[0]:   RDERR has   ** Error **
C66xx_0: GEL Output: DX1GSR0[25]:   QSGERR on Rank1 has ** No Error **
C66xx_0: GEL Output: DX1GSR0[24]:   QSGERR on Rank0 has ** Error **
C66xx_0: GEL Output: DX1GSR0[6]:    WLERR has   ** No Error **
C66xx_0: GEL Output: Byte Lane 2:
C66xx_0: GEL Output: DX2GSR2[6]:   WEERR has   ** No Error **
C66xx_0: GEL Output: DX2GSR2[4]:   REERR has   ** No Error **
C66xx_0: GEL Output: DX2GSR2[2]:   WDERR has   ** No Error **
C66xx_0: GEL Output: DX2GSR2[0]:   RDERR has   ** Error **
C66xx_0: GEL Output: DX2GSR0[25]:   QSGERR on Rank1 has ** No Error **
C66xx_0: GEL Output: DX2GSR0[24]:   QSGERR on Rank0 has ** Error **
C66xx_0: GEL Output: DX2GSR0[6]:    WLERR has   ** No Error **
C66xx_0: GEL Output: Byte Lane 3:
C66xx_0: GEL Output: DX3GSR2[6]:   WEERR has   ** No Error **
C66xx_0: GEL Output: DX3GSR2[4]:   REERR has   ** No Error **
C66xx_0: GEL Output: DX3GSR2[2]:   WDERR has   ** No Error **
C66xx_0: GEL Output: DX3GSR2[0]:   RDERR has   ** Error **
C66xx_0: GEL Output: DX3GSR0[25]:   QSGERR on Rank1 has ** No Error **
C66xx_0: GEL Output: DX3GSR0[24]:   QSGERR on Rank0 has ** Error **
C66xx_0: GEL Output: DX3GSR0[6]:    WLERR has   ** No Error **
C66xx_0: GEL Output: Byte Lane 4:
C66xx_0: GEL Output: DX4GSR2[6]:   WEERR has   ** No Error **
C66xx_0: GEL Output: DX4GSR2[4]:   REERR has   ** No Error **
C66xx_0: GEL Output: DX4GSR2[2]:   WDERR has   ** No Error **
C66xx_0: GEL Output: DX4GSR2[0]:   RDERR has   ** Error **
C66xx_0: GEL Output: DX4GSR0[25]:   QSGERR on Rank1 has ** No Error **
C66xx_0: GEL Output: DX4GSR0[24]:   QSGERR on Rank0 has ** Error **
C66xx_0: GEL Output: DX4GSR0[6]:    WLERR has   ** No Error **
C66xx_0: GEL Output: Byte Lane 5:
C66xx_0: GEL Output: DX5GSR2[6]:   WEERR has   ** No Error **
C66xx_0: GEL Output: DX5GSR2[4]:   REERR has   ** No Error **
C66xx_0: GEL Output: DX5GSR2[2]:   WDERR has   ** No Error **
C66xx_0: GEL Output: DX5GSR2[0]:   RDERR has   ** Error **
C66xx_0: GEL Output: DX5GSR0[25]:   QSGERR on Rank1 has ** No Error **
C66xx_0: GEL Output: DX5GSR0[24]:   QSGERR on Rank0 has ** Error **
C66xx_0: GEL Output: DX5GSR0[6]:    WLERR has   ** No Error **
C66xx_0: GEL Output: Byte Lane 6:
C66xx_0: GEL Output: DX6GSR2[6]:   WEERR has   ** No Error **
C66xx_0: GEL Output: DX6GSR2[4]:   REERR has   ** No Error **
C66xx_0: GEL Output: DX6GSR2[2]:   WDERR has   ** No Error **
C66xx_0: GEL Output: DX6GSR2[0]:   RDERR has   ** Error **
C66xx_0: GEL Output: DX6GSR0[25]:   QSGERR on Rank1 has ** No Error **
C66xx_0: GEL Output: DX6GSR0[24]:   QSGERR on Rank0 has ** Error **
C66xx_0: GEL Output: DX6GSR0[6]:    WLERR has   ** No Error **
C66xx_0: GEL Output: Byte Lane 7:
C66xx_0: GEL Output: DX7GSR2[6]:   WEERR has   ** No Error **
C66xx_0: GEL Output: DX7GSR2[4]:   REERR has   ** No Error **
C66xx_0: GEL Output: DX7GSR2[2]:   WDERR has   ** No Error **
C66xx_0: GEL Output: DX7GSR2[0]:   RDERR has   ** Error **
C66xx_0: GEL Output: DX7GSR0[25]:   QSGERR on Rank1 has ** No Error **
C66xx_0: GEL Output: DX7GSR0[24]:   QSGERR on Rank0 has ** Error **
C66xx_0: GEL Output: DX7GSR0[6]:    WLERR has   ** No Error **
C66xx_0: GEL Output: Byte Lane 8:
C66xx_0: GEL Output: DX8GSR2[6]:   WEERR has   ** No Error **
C66xx_0: GEL Output: DX8GSR2[4]:   REERR has   ** No Error **
C66xx_0: GEL Output: DX8GSR2[2]:   WDERR has   ** No Error **
C66xx_0: GEL Output: DX8GSR2[0]:   RDERR has   ** Error **
C66xx_0: GEL Output: DX8GSR0[25]:   QSGERR on Rank1 has ** No Error **
C66xx_0: GEL Output: DX8GSR0[24]:   QSGERR on Rank0 has ** Error **
C66xx_0: GEL Output: DX8GSR0[6]:    WLERR has   ** No Error **
C66xx_0: GEL Output: ****************************************************************************************************************

0 Larry McCrigler over 7 years ago in reply to Larry McCrigler

Prodigy 210 points

I am working thorough the Debug Spreadsheet. In the interest of providing as much information as possible relating to the problem, Here is a link to the spreadsheet values we have at the moment.

www.uslinc.com/.../USL_KS2_DDR_Debug_Spreadsheet_v1_01.xlsx

0 Larry McCrigler over 7 years ago in reply to Larry McCrigler

Prodigy 210 points

Today I decided to re-configure for slower speed (DDR-1066) and redo the testing. I seem to get the same results. Here is a link to the Debug Spreadsheet with the current information and logs. I don't see anything wrong with the configuration, but I will dig into the values impedance next. Then I'll use the scope to verify the hardware, especially the clocks.

www.uslinc.com/.../USL_KS2_DDR_Debug_1066_Test.xlsx

0 Larry McCrigler over 7 years ago in reply to Senthilkumar Srinivasan

Prodigy 210 points

0 Senthilkumar Srinivasan over 7 years ago in reply to Larry McCrigler

TI__Mastermind 43660 points

Larry,

Thanks for the update. It seems like there is no issue with the configuration. You may need to verify the hardware interface, length matching and design guidelines.

Regards,
Senthil

0 Larry McCrigler over 7 years ago in reply to Senthilkumar Srinivasan

Prodigy 210 points

Senthil,

I have resolved the issue we've had with the DDR3. It seems the configuration was correct, but our prototype does not support ECC. Even though I set ECC to disabled in the spreadsheet, the EVMK2E GEL needs to be manually edited to turn off ECC. The Global Default Setup script leaves ECC set ON which is the cause of the problems we're having.

We've edited the GEL to turn off ECC and we're good to go.

Thanks for all the support.

Larry McCrigler

0 Senthilkumar Srinivasan over 7 years ago in reply to Larry McCrigler

TI__Mastermind 43660 points

Glad to know that you resolved the issue. Thanks for your update.

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K2E DDR3 Debug GEL failed to read memory for EMIF Report