Sending monolithic buffers from DDR fails from (apparent) caching problem

Hi Philip,

I've contacted the TCI6638K2K design team. They should respond directly here.

Best Regards,
Yordan

Philip Taylor,

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Philip

1. When you say that it works if the buffer is not in DDR, did you try to put the buffer in MSMC memory?

2. Have you changed the MPAX or the SES/SMS registers at all?

3. can you try to do call back to L2 cache as well (CACHE_wbL2) ?  Please try it and report your results

Regards

Ran

Hello Ran,

My answers to your questions are inline:

1. When you say that it works if the buffer is not in DDR, did you try to put the buffer in MSMC memory?
A. I have jsut tried that but it failed the same way, reporting it had sent the data, but it never being received by the waiting core

2. Have you changed the MPAX or the SES/SMS registers at all?
A. I don't think I have changed any of these.

3. can you try to do call back to L2 cache as well (CACHE_wbL2) ?  Please try it and report your results
A. I have added the write back L2 as well, immediately after my L1 call back, just before the descriptor is pushed to the Tx queue (shown below)
This did not have the desired effect, as the next core still fails to receive the SRIO message.

//Flush the memory region, to ensure it is written to DDR
CACHE_wbL1d ((void *) &mono_region[0], NUM_Rx_MONO_DESC * NUM_CORES * SIZE_MONO_DESC, CACHE_FENCE_WAIT); //or CACHE_FENCE_WAIT?
CACHE_wbL2 ((void *) &mono_region[0], NUM_Rx_MONO_DESC * NUM_CORES * SIZE_MONO_DESC, CACHE_FENCE_WAIT); //or CACHE_FENCE_WAIT?
/* OSAL Hook: Once the descriptors have been populated; let the OSAL know that we are done. */
Srio_osalEndDescriptorAccess ((Srio_DrvHandle)ptr_srioDrvInst, (void *)ptrMonoDesc,
          ptr_srioDrvInst->txDescSize);
/* Push the transmit buffer descriptor into the Transmit Queue. */
Qmss_queuePushDescSize (ptr_srioDrvInst->txQueue, (uint32_t*)hDrvBuffer, ptr_srioDrvInst->txDescSize);

Thank you for your time.

Philip Taylor

One more suggestion

I wonder what happens if you disable cache on the receive core and try again. Let's see if this is send issue or receive issue.

(This will not explain why when you disabled cache on the send everything worked, but let's try)

Thanks a lot


Ran

Hi Ran,

Sorry for the delay in replying, I was on leave.

I was originally disabling caching in the DDR globally using the following line in the app.cfg file:
Cache.setMarMeta(0xA0000000, 0x40000000, 0);

To implement your requested change, I moved the setting of the MAR value from the cfg file to the C code. At the start of the multicoreTestTask function I added the following lines:
extern "C" Void multicoreTestTask(UArg arg0, UArg arg1)
{
    coreNum = CSL_chipReadReg (CSL_CHIP_DNUM);

    //Disable the caching JUST on the (first) receiving core
    if ( coreNum == (FIRST_TX_CORE+1) )
    {
     //From sprugw0c
     //0184 8280h, MAR160, Memory Attribute Register 160, A000 0000h - A0FF FFFFh
     volatile uint32_t* MAR160 = ( volatile uint32_t*)0x01848280; //  This is MAR 160 => A000 0000h - A0FF FFFFh
     TRACE(info,"About to disable caching on core " << coreNum << " with MAR160 = " << *MAR160);
     CACHE_disableCaching (160);
     TRACE(info,"Finished disabling caching on core " << coreNum << " with MAR160 = " << *MAR160);
    }
The output of this code suggested that the bottom bit was changing:
[C2] ../main.cpp(1050) : About to disable caching on core 2 with MAR160 = 13
[C2] ../main.cpp(1052) : Finished disabling caching on core 2 with MAR160 = 12

However this didn’t work. I tried applying this change to all cores, but it still didn’t work.

Is this the correct way to disable the caching on a per core basis?

I only set MAR 160 as this covers more memory than I am using for my small buffer in this simple test, and the MAP files shows this allocated at the start of the buffer (i.e. at 0xA000 0000)

Thank you for your help.

Philip Taylor