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RFSDK custom signal

Other Parts Discussed in Thread: DAC38J84, RFSDK, ADC32RF45, ADC32RF80, DAC38J84EVM

Hello,

I’m trying to test the RFSDK (demo4 – DAC38j84 & ADC32RF45) with a custom signal. I'm using the RFSDK version 2.0.6.

I have some questions on the process:

  1. I don’t have the K2L-HSP FMC adapter card. Is it a must? Or can I use the second Lamarr JESD lane? What are the difference in configuration? How do I connect the cards in this configuration?
  2. I was given a Python script and a cfg file that are designed for LTE60 in order to create a custom signal. Demo 4 is using LTE75, is it an issue or will it work just the same?
  3. When I’m using the JESDlpbk configuration I see that I managed to load the custom signal into the TX DSP but the TX DFE shows nothing. What might be the reason for that? How can I fix it?
  4. When I’m using the normal demo4 configuration I receive this message in the command prompt:

root@k2l-evm:/usr/share/radio/tests# radio on 18300 300

Turn the AFE on, and check its JESD RX status. Then press RETURN.

Traceback (most recent call last):

  File "/usr/bin/radio", line 108, in <module>

    command.onecmd(' '.join(sys.argv[1:]))

  File "/usr/lib/python2.7/cmd.py", line 221, in onecmd

    return func(arg)

  File "/usr/lib/python2.7/rfsdk/command.py", line 1161, in do_on

    self.radio.radio_on(ul, dl)

  File "/usr/lib/python2.7/rfsdk/radio.py", line 466, in radio_on

    self.dfe.dfe_on_rx()

  File "/usr/lib/python2.7/rfsdk/platform/TCI6630K2L.py", line 195, in dfe_on_rx

    self.dfeS.DfeStartRx(0)

  File "/usr/lib/python2.7/dfe/service.py", line 478, in DfeStartRx

    raise rfsdk.Error('dfeService.DfeStartRx() API call failed with status %r (%d)' % (status, result,))

rfsdk.Error: dfeService.DfeStartRx() API call failed with status 'RFSDK_API_RESULT_DFESVC_JESDRX_SERDES_LANE0_TIMEOUT' (42).

I also receive this message (42) when trying to use the GUI option.

I configure the DAC38J84 using the cfg files provided in the RFSDK. How do I configurate the ADC32RF45 and how do I connect it, is there a guide or documentation on the subject? Which configuration file to use?

5. What are the memory address for each step of the demo?

Thanks in advance,

  • Welcome to the TI E2E forum. I hope you will find many good answers here and in the TI.com documents and in the TI Wiki Pages (for processor issues). Be sure to search those for helpful information and to browse for the questions others may have asked on similar topics (e2e.ti.com). Please read all the links below my signature.

    We will get back to you on the above query shortly. Thank you for your patience.

    Note: We strongly recommend you to create new e2e thread for your queries instead of following up on an old/closed e2e thread, new threads gets more attention than old threads and can provide link of old threads or information on the new post for clarity and faster response.

  • I managed to go forward and now I get this message:
    root@k2l-evm:~# radio on 18300 300
    Traceback (most recent call last):
    File "/usr/bin/radio", line 108, in <module>
    command.onecmd(' '.join(sys.argv[1:]))
    File "/usr/lib/python2.7/cmd.py", line 221, in onecmd
    return func(arg)
    File "/usr/lib/python2.7/rfsdk/command.py", line 1161, in do_on
    self.radio.radio_on(ul, dl)
    File "/usr/lib/python2.7/rfsdk/radio.py", line 398, in radio_on
    self.afe[0].jesdConfigure(jesd)
    File "/usr/lib/python2.7/afe/service.py", line 106, in jesdConfigure
    raise exception
    rfsdk.Error: afeService.jesdConfigure() API call failed with status 'AFE_INVALID_JESD_PARAMETER' (8)
  • Hi Eran,

    We are looking into to the questions related to changing the test signal. Please note that you need to have the K2L-HSP FMC adapter card to connect the ADC and DAC EVMs with the 66Ak2L EVM and run a complete DAC to ADC loopback (i.e. non-JESD loopback configuration). You mentioned that you have the TI Design Demo working as expected. Did you mean the JESD loopback or the full 66AK2L+DAC+ADC Demo, since the complete demo cannot run without the K2L-HSP FMC adapter EVM.

    Regards

    -Nitin

  • Hello, 

    Here are some answers for your questions.   Nitin will forward to you the zip file, with the complete example, using JESDloopback.   To run with the (2) data converter EVMs you will need the DLC card and its software also.  There is a word file with the procedure and expected results.

    1. I don’t have the K2L-HSP FMC adapter card. Is it a must? Or can I use the second Lamar JESD lane? What are the difference in configuration? How do I connect the cards in this configuration?

           In order to run demo4, the customer is expected to have a Rev2 DLC card and its software.  All 4 JESD Tx and 4 JESD Rx lanes  are used on CN16 (first    

           Lamarr EVM FMC connector).   This is illustrated in the demo(design)4 Getting Started Guide.

     

    2. I was given a Python script and a cfg file that are designed for LTE60 in order to create our custom signal. Demo 4 is using LTE75, is this an issue or will it work just the same?  

    The 92.16Msps BBsample rate has been given the LTE60 name.  However LTE75 is actually the same sample rate, the files should be OK.  I have provided a more complete example, and demonstrated this using the JESDloopback (ie no DLC or data converter EVM required).          The new instructions, test report are in a follow up email.

    3.When I’m using the JESDlpbk configuration I see that I managed to load our custom signal into the TX DSP but the TX DFE shows nothing. What might be the reason for that? How can I fix it?

     The webpage, captures for DFE@Tx, DFE@rx/Fdbk – random 4K samples from DFE.  (may not display TDD data properly).   The webpage, captures for DSP@BBTx, DSP@BBRx – the first 4K samples time synchronized to DL sync.  (your Tx and Rx data have to be within first 4K samples to show on web display)

     If you are using a TDD gated waveform, the capture for this display is random, works for FDD  not TDD.   You can capture the DSP @ BBRx, and see if that captures, or follow the scripts in the new email to capture the full 10ms BBRx data and analyze it.   

    4. When I’m using the normal demo4 configuration I receive this message in the command prompt:

     The demonstration uses Lamarr EVM <-> DLC card <-> ADC32RF80(45)

                                                                                                  <-> DAC38J84EVM

    If you only have one dataconverter hooked up directly, the other one will have JESD errors at Radio on.

    Regards,

    Joe Quintal

  • Thank you for your answer.

    I got the K2L-HSP FMC adapter and the guide but I don't have the adapter card's GUI. The user guide directs me to the E2E for help.

    Could you share a link for downloading the GUI?


    Thanks,

  • Hi Eran,

    We are working on releasing the latest version of the K2L-HSP FMC adapter GUI so in the meantime, I'll provide the unreleased version to your local TI contact and ask him to get in touch with you. I'll also provide the QPSK signal JESD loopback example Joe mentioned in his response earlier.

    Regards
    -Nitin
  • Nitin,


    Here are the version information of the Lamarr EVM:

    Here is the error that I'm getting with the DLC card (both in the CMD & GUI) while using normal RFSDK demo 4:

    another two questions are about the ADC32RF45 card:

    1. Can I use the ADC32RF80 CFG files with it or I need different files? Because after loading the ADC32RF80 CFG files I'm not getting the same values that I was suppose to get according to the guide in the DDC Configuration tab (after pressing read all in the Low Level View).

    2. What LEDs are supposed to light on the ADC after configuration? -just to make sure its configured correctly.

    Thanks,

  • Hi Eran,

    As discussed earlier, the TX1 and TX2 JESD lanes are swapped on Rev 2.0 EVM. There are two ways to workaround this:

    (1) Hardware Mods to rewire the lanes on a rev 2 EVM or

    (2) Lane reassignment in the DAC configuration.

    Going with option 2, I have attached a modified DAC38J84 config to work with Rev 2.0 Lamarr EVM. Please use this for the DAC low level configuration (step 9 of section 3.1.3: DAC38J8x EVM GUI).

    Regarding your second question: We have tested the demo with the ADC32RF80 configuration files listed in the Getting Started Guide. Can you please try it out with the complete setup once the JESD errors go away with the attached DAC config? I'll check the LED settings from a working setup and let you know.

    Regards

    -Nitin

    K16_Lamarr_rev2_737p28.cfg

  • Nitin,

    Thank you for your help.

    I've used the new cfg but I'm still getting the same error:

    Could you please advise? -Please note that my EVM version is: 1.0.2.1.

    Thanks,

    Eran.

  • Hi Eran,

    We're looking into this and will get back to you asap. Thanks for your patience.

    Regards

    -Nitin

  • Hi Eran,

    Please try the following:

    1. Run the stock design-4 setup using the RFSDK Web GUI instead of the scripts. (I would highly recommend re-installing the MCSDK and RFSDK on the Lamarr EVM to start from a clean state).

    2. Please make sure to reload the RFSDK GUI webpage every time you restart the EVM (even if the IP of the EVM doesn't change between reboots). Close and re-open the browser every time the EVM is rebooted.

    3. After you select the Design-4 demo option on the RFSDK GUI main landing page, please check if the following file is getting created in the /tmp directory.

    /tmp/rfsdk_stubbed_afe (The GUI creates this file ever time the board is rebooted as /tmp is a volatile filesystem. To ensure this, the GUI page needs to be hard reloaded every time).

    The error you're getting is not related to JESD issue with Demo-4 (though we did need the DAC config for rev-2 EVM due to TX lane swap). This error indicates that the wrong demo (Small Cell Demo) is getting invoked as the AFE service is not used by any other demo except the small cell demo. This will happen if the above file is not getting created in the /tmp directory.

    Regards

    -Nitin 

  • Hello Nitin,

    I reinstalled the MCSDK & RFSDK on the EVM as you suggested (please note that I chose: lamarr-evm-demo4-mcsdk3147 default as the Target Board Configuration).

    These are the files that the GUI creates when loaded after boot:

    After reinstalling the RFSDK I get this error when trying to turn radio on:

    What could be the problem now?

    Thanks,

    Eran.

  • Hi Eran,

    The JESDRX_SERDES_LANE_TIMEOUT points towards a problem on the ADC side. You mentioned earlier that the values you read back after programming the ADC32RF45 EVM were not the same as given in the DDC configuration tab in the getting started guide, This should not be the case and indicates that the ADC is not being programmed correctly.

    1. Please confirm the version of your ADC32RFxx EVM configuration GUI? Here's what I have on my setup.:

    Version information: 2.0

    Build date: 7/23/15

    2. We have seen that having more than one GUIs open at the same time (ADC, DAC, DLC) may cause issues with the GUI(s) which can lead to programming errors. Please run only one GUI at a time and close it after programming the corresponding device. Also, please make sure that the correct power-up sequence is followed.

    3. Try running the ADC GUI on a different PC if possible and see if you read back the values as expected?

    Regards

    -Nitin 

  • As the release of RFSDK 2.0.6, the test was done with a preliminary version of ADC32RFxx revD GUI.

    Now we installed the released revD GUI version from ti website to be consistent with customer. The first program after installation did show issue that register didn't seem to be populated. Press the "Read All" button again and it worked. After that, tried about 10 times to repeat, didn't see the issue again.

    We will continue monitor it and report to design team if it shows up again. An indication of the register values are writtin in is to check DDC Configuration page. Both CHA DDC EN and CHB DDC EN should be checked. The DDC NCO values are not zero. Please reference the GSG document figure ADC32RFxx EVM GUI ADC tab.

    Regards,

    Michelle

  • Hello Nitin,


    The version info for the GUI:

    I tried reinstalling the GUI on my computer and on a different computer, but got the same results. I don't get the same values as the guide, no matter how many times I press read all at the Low Level View tab and I only open one GUI at a time.

    Please note that I tried to configure the card using a different cfg file (one that came with the GUI for the ADC32RF45 and uses an internal clock) and managed to get the PLL2 locked led to light (which probably means I'm able to configure it).

    While I'm programming the card using the RFSDK files for the ADC32RF80 I don't get any locked led indication on my ADC32RF45 (beside the power led which lights).

    Best Regards,

    Eran.

  • Eran,

    On my EVM, only power led was on. The LEDs for the clocks are not on either. But mine is working fine.

    What kind of EVM do you have? Mine is ADC32RF80 which has DDC enabled.

    Regards,

    Michelle

  • Eran,

    Also please send the rev number of the EVM.

    In terms of the clock connection, please follow the GSG and to make sure J5 and J7 on ADC EVM are connected with clock input:
    "Use two length-matching SMA cables, one to connect from J15 of the DLC to the LMK CLKIN (J7) of the ADC32RFxx EVM; one to connect from J16 of the DLC to the ADC CLK IN (J5) of the ADC32RFxxEVM"

    Before loading different configuratios to DLC, USB cable should be unplugged to do a full power cycle.

    Regards,
    Michelle
  • Eran,

    Here's the updated ADC setup guide. It's using rev D GUI downloaded from ti.com. The steps should be the same as the doc you have but the GUI snapshots are updated. You can ignore the wideband part and only focus on mid-band demo.

    Thanks and Regards,

    Michelle66AK2L06_Design4_GSG_ADCsection.pdf

  • Hello Michelle,

    I'm using the ADC32RF45 card (PCB REV D and 4 is written on the chip itself) and the clk cables are connected as you described. The DLC card has 2 green lock LEDs and the only LED on the ADC card that is on is the power LED.

    I followed your guide but after pressing the read all I never get CHA and CHB DCC EN selected no matter how many time I press it or reconfigure the card.

    Thank you for your assistance,

    Eran.

  • Eran,

    I know for sure that ADC32RF80 has DDC enabled. ADC32RF45 however can havd DDC by-passed. Where did you get the ADC EVM?
    I've sent email to ADC app engineer to confirm.

    Thanks and Regards,
    Michelle
  • Michelle,

    I got it from TI's representative, Eastronics.

    Best regards,
    Eran.
  • Eran,

    Got feedback from ADC engineer and here are two things we need you to help check:

    1. For ADC32RF45, if it's pre-production, it's DDC by-pass mode only. However, the final silicon of ADC32RF45 supports both bypass and DDC modes. To determine what version.  The lot trace code marking on the top of the ADC right under the part number is what we would need to see to know if the device is preproduction silicon and if it is whether the device is bypass only mode or DDC only mode. Please take a snapshot and send to us.

    2. If the SPI programming of the ADC fails and they always read back zero from all the page registers, then likely the ADC is not seeing SYSREF or the sample clock.   The common mode voltage of SYSREF changed going to final silicon, and if that is wrong on the hardware then you will fail to configure the ADC. When you read back the register value, are they all zero?

    Thanks and Regards,

    Michelle

  • Michelle,

    Yes I do get all zero & here are the snapshots you wanted:


    Best regards,

    Eran.

  • Hi Eran,

    While we are waiting for response on the ADC version, there's another way to help determin if it's a clock issue.

    If you have a signal generator, set freq to 2949.12MHz, connect the output to a power splitter (make sure bandwidth won't attenuate the signal), the output of the power splitter connect to J5 and J7 respectively.

    Set signal power to be 2dBm or higher, try program ADC. (no need to program DLC/DAC...)

    If this one works -- ADC register non-zero and the DDC tab show CHA CHB are selected, it's gonna be a clock issue.

    On my side, 2dBm works fine. -6dBm, program failed.

    If you don't have a signal generator/power splitter, just make sure the SMA cables for clocks are matched and working well.

    Thanks and Regards,
    Michelle
  • Hello Michelle,

    I've tested the card with the signal generator and still got all zero.

    The cables that I'm using are matched and have attenuation of ~1.2-1.3dB @ 3GHz.

    Thanks,

    Eran.

  • Eran,

    We have got confirmation that the one you have is the final silicon. It's not clear why you have difficulty programming ADC. Nitin will contact you regarding replacing/sending new board.

    Here's a few things I can think of for you to double check:

    1. Make sure GUI is downloaded from TI.com (latest revD). Use config in the "DDC Mode" folder
    2. Make sure to push SW1 to reset ADC before loading ADC cfg
    3. May try setting clock from signal generator 6 dB higher
    4. Registers to read are under ADCxxx group and the values are listed in the 6th column of register map
    5. When registers are zero, ADC32RFxx -- DDC configuration Channel is not selected as well?
    6. Is the board being power cycled between tests?

    Sorry if none helps. We'll hope new board you'll receive work then.

    Thanks and Regards,
    Michelle
  • Hello Michelle,

    About the double check:

    1. OK.

    2. OK.

    3. Tried, didn't help.

    4. They are all zero.

    5. not selected.

    6. Yes. But not after I'm trying to reconfigure the ADC.

    Thank you for your assistance up until now. I will wait for the new board and update here if necessary.

    Best regards,

    Eran.

  • Hello Michelle & Nitin,

    I've received the ADC32RF80, I can now configure it and it seems that the demo is working properly with no errors.

    I've tried testing the custom signal according to your document. The loop-back is working well according to the document. But, the part that we're interested in is to test the custom signal after the entire RF loop as well (DAC-ADC RF loop). I'm unable to receive good results (I don't get any signal in the RX with the custom signal not being in loop-back mode) even though the normal demo4 of the RFSDK is working properly (I see RX results as expected with the RFSDK). Could you please give me some instructions on how to properly do that?

    Thank you,

    Eran.

  • Hello Eran,

    In order to help you isolate the problem..

    a) when you run the standard Demo4 on the DAC, do you have 

         you can look at the webpage Tx, this is the DPD input capture (1*)

          the spectrum analyzer Tx output plot, please capture (2*)

          when the DAC output -> filtered -> ADC input

          the ADC downconverts RF to IF, the Rx and Feedback DFE convert IF to 0IF, to the BBRx outputs.

          (note in FDD waveforms, you can see the BBRx on the webpage 3*)

          after capturing the BBRx 10ms data,  for each channel, ("playback capture" in RFSDK User Guide), you copy the files created to a host PC, and analyze the

          BBRx data, you can evaluate the spectrum and time series of the data 4*)

    b)   when you are doing the JESD loopback, there is no analog output.   

          if this is an FDD signal you can use the webpage 1*

          if this is an FDD signal you can use the webpage 3*

          you can do a playback capture, and plot the 10ms data 4*

    c)  Custom waveform, this is a TDD waveform, the Tx out (1*) may not work do to when we collect the capture buffer,

          if the DAC configuration is correct, you should have with a 10ms period, and triggering the spectrum analyzer on envelope of the signal, you should capture

           a Tx output.   the web display of BBRx (3*) may not work becuase we are looking at 4K of data, possibly while Tx is not on.

          if you do the playback capture command, collect the files, (4*)  if you had a DAC output, and the cable and filter are still there for ADC, we expect to have a 

          gated (TDD) Rx signal.

    I have included a matlab script, you need to setup the source file(infilenameIQ), path(directoryin), sample rate (Fs)

        Please send the pictures of this is not working.

        When you have demo4 running, you can just add the playback load command from the RFSDK. 

    readIQfile_plotTS_FFT_CCDFwbin.zip

        Regards,

    Joe Quintal

  • Hello Joe,

    I've tired activating the cards a few times (in normal demo4 & JESD loopback mode) and here are my observations:

    1. I saw on a spectrum analyzer that the DAC is transmitting the signal .

    2. I don't have any low pass filter between the DAC-ADC is it a must? if so, should have I received one from you with the cards? if not, what are the specification for the LPF- the demo4 manual specify 120MHz in one place and 265MHz in another.

    3. Other then the filter the cards are configured according to the manual (The EVM's SW show the same values as in the manual screenshots).

    4. The RX (RX signal capture @ DSP) output isn't always as expected- only once it showed me the correct signal - but that might have been a fluke, sometimes it shows junk but most of the time it show nothing (maybe the result of me not having the LPF).

    5. Attached is the configuration for the ADC - so you can make sure I configurated the card correctly):

    6. Attached is an example of demo4 TX DFE output:

    Thank you for your help,

    Eran.

  • Hello,

    The only change for the custom signal, is to substitute the baseband data for the BBTx input, and to show a method to playback capture the BBRx output.   If the process has worked, then you are ready for your own experiments.

    In general an ADC input even an RF sampling one, needs to have an input filter.   You can do experiments without a filter, but this is not going to give the best possible results.   If you have a specific RF center frequency and bandwidth, there are several suppliers of bandpass filters for this.

    As I stated in the last information sent, you need to do a playback capture for the BBRx data to collect the entire sample set.  The RFSDK webpage displays has a RANDOM capture.   You have a pulse waveform, if the RFSDK captures during the time the Tx waveform is OFF you will get an indication of no signal.

    You need to follow the BBRx playback capture script I sent (or Nitin sent), it captures the 10ms data.   You should always see the BBRx signal in the playback capture.

    Regards,

    Joe Quintal

  • Joe,

    In normal demo4 mode I see no signal in the RX (I saw a very weak signal only once and nothing during the other times I tried). I tried to use the scripts but I receive nothing in the matlab (all zero) as well.

    I see, using the spectrum analyzer, that the DAC is transmitting signal and that the ADC is configurated as it should in it's GUI.

    Best regards,

    Eran.

  • Hello Michelle & Joe,

    I tried programming the ADC after pressing the ADC reset on the GUI.

    Now I receive data from the ADC but it's noise:

    What do you make of this?

    Regards,

    Eran.

  • Hi Eran,

    What did you do differently this time? This can give us a clue of the problem.

    Can you use the shell script given during webex session to check JESD status? 

    When nothing was captured, we saw JESD RX FIFO error. With some noise data, the JESD status could change, let us know.

    Another thing: remember you showed that the ADC GUI do not save the clock/NCO number after GUI is closed?

    Here's what I saw on my PC: after ADC is programmed and clock/NCO all set, GUI is closed. Then I re-open it. The default sample rate is 3000, so I need to re-type 2949.12, once this is typed, NCO values are automatically updated. This latter part, I don't remember seeing on your PC. Please confirm. 

    I saved the cfg after I made sure everything is working. I attached the cfg here. Please also save your cfg after following user-guide ADC program procedure. You can compare to see if there's difference or send the cfg file to us.

    Thanks and Regards,

    Michelleadc32rfxx_save.cfg

  • Eran,

    Another concern is the clock output from DLC board. Can you measure the power level from J15 and J16 respectively? For your reference, I got -4.2dBm from each port.

    Thanks and Regards,
    Michelle
  • GSG_Lamarr_ADC32RFxx.docxEran,

    In discussing with HSP team, the ADC32RF80 EVM has high power input requirement for clock source. Although -4dBm clock worked in our system, it's at a marginal level. To minimize the loss, the SMA cable used for clock should be short and thick.

    There's another way to eliminate DLC clock to ADC. It's using external signal generator to provide clocks to ADC. The whole system need to be synced so 10MHz from signal generator will be the input to Lamarr clock chip. I tested and put together a document describing how to run the test.

    Please follow the procedure in previous emails before starting this method.

    Regards,

    Michelle

  • Hello Michelle,

    Sorry for the delay, I was away for work in the past 2 weeks.

    In order to get these results I pressed ADC reset in the ADC GUI.

    It seems that I still get the same error even with receiving noise in the RX at the RFSDK GUI:

    I measured on the DLC: J15 - (-3.9dBm), J16 - (-3.7dBm).

    As for your last recommendation, it will take me some time to acquire this splitter, in the mean time I would appreciate if you could check if this test will work on the LAMMAR EVM V2 or do I need to perform any change to it.

    Thank you and best regards,

    Eran.

  • Hello Michelle,

    Attached is MY ADC cfg file.

    Best adc32rfxx_eran.cfgregards,

    Eran.

  • Michelle,

    After trying to configure the ADC & DAC. I think the problem is in the JESD configuration.

    If I follow the DEMO4 guide (I first configure the DAC and then the ADC) I get write stub error.

    If I configure the DAC again after the ADC I don't get that error but I don't see anything in the RX and the ADC JESD configuration is corrupted (all zero).

    I think the problem is me using the Lamarr V2 which has different layout to the JESD. This causes me to use a different configuration file for the DAC which the ADC JESD configuration doesn't support (perhaps an issue with the SysRef specifically).

    In this case I think we have 2 options: either using a different ADC configuration file (if you could supply one) which supports the Lamarr V2 or arrange for me to use the Lamarr V3.

    I would appreciate you looking into this theory.

    Best regards,

    Eran.

  • Eran,

    When you configure DAC, you will need to press the 3rd button on the front page, otherwise you'll have JESD TX error. We didn't have this problem, but I put that in the latest GSG attached. TIDUC58.pdf

    When the DAC is correctly programmed, you'll still have RX JESD error which you can run the jesd status check script to verify.

    The difference between rev2 and rev3 is on the tx lane mapping, that's why we need different configuration files for the DAC. However, RX side is mapped the same and therefore I don't think you'll need a different configuration file.

    The reason I ask to check the clock power level is because I suspect the JESD RX error is caused by the clock. So far, we've got confirmation from ADC support team that the program config you sent is OK except you may have different DDC NCO setting. I know that a rev3 is on the way but I encourage you do follow my previous post on checking clock and try using external clock. I could be wrong but I'm not positive that new rev3 EVM will fix your problem.

    Thanks and Regards,

    Michelle

  • Hello Michelle,

    After replacing the Lamarr to V3, I don't get the JESD errors.

    JESD.txt
    -----------------------------------------------------------------------
    Reading Lamarr JESD SERDES status regs
    -----------------------------------------------------------------------
    
    LANEx_CTL_STS regs - RX_OK=bit1, RX_LOSS=bit0
    
    JESD LANE0_CTL_STS (0x02325FE0)
    0xF2C0F2F2
    
    JESD LANE1_CTL_STS (0x02325FE4)
    0xF2C0F2F2
    
    JESD LANE2_CTL_STS (0x02327FE0)
    0xF2C0F2F2
    
    JESD LANE3_CTL_STS (0x02327FE4)
    0xF2C0F2F2
    
    JESD_SERDES PLL_CTRL regs - TX_PLL_OK=bit28, RX_LN_1_0_OK=bits9_8, RX_LN_1_0_SD_                                                                                                                                                             STATE=bits1_0
    
    JESD_SERDES_0 PLL_CTRL (0x02325FF4)
    0xF0000303
    
    JESD_SERDES_1 PLL_CTRL (0x02327FF4)
    0xF0000303
    
    
    -----------------------------------------------------------------------
    Reading Lamarr DFE JESD-RX regs
    -----------------------------------------------------------------------
    
    JESDRX_LANE0_CFG (0x25D41404)
    0x00000101
    
    JESDRX_LANE1_CFG (0x25D41408)
    0x00000301
    
    JESDRX_LANE2_CFG (0x25D4140c)
    0x00000201
    
    JESDRX_LANE3_CFG (0x25D41410)
    0x00000001
    
    JESDRX_FIFO_FLAG/LANE_ERROR_LANE0 (0x25D41C08)
    0x00000000
    
    JESDRX_FIFO_FLAG/LANE_ERROR_LANE1 (0x25D41C48)
    0x00000000
    
    JESDRX_FIFO_FLAG/LANE_ERROR_LANE2 (0x25D41C88)
    0x00000000
    
    JESDRX_FIFO_FLAG/LANE_ERROR_LANE3 (0x25D41CC8)
    0x00000000
    
    JESDRX_CS_STATE (0x25D40030)
    0x00002222
    
    JESDRX_FS_STATE (0x25D40034)
    0x00001111
    
    JESDRX_SYSREF_ERR (0x25D42008)
    0x00000000
    
    JESDRX_ERR_CNT_LINK0 (0x25D41830)
    0x00000000
    
    JESDRX_ERR_CNT_LINK1 (0x25D41870)
    0x00000000
    
    JESDRX_SKEW_LINK0 (0x25D4182C)
    0x00000001
    
    JESDRX_SKEW_LINK1 (0x25D4186C)
    0x00000000
    
    -----------------------------------------------------------------------
    Reading Lamarr DFE JESD-TX regs
    -----------------------------------------------------------------------
    
    JESDTX_LANE0_CFG (0x25D01404)
    0x00000001
    
    JESDTX_LANE1_CFG (0x25D01408)
    0x00000101
    
    JESDTX_LANE2_CFG (0x25D0140c)
    0x00000200
    
    JESDTX_LANE3_CFG (0x25D01410)
    0x00000300
    
    JESDTX_FIFO_FLAG_LANE0 (0x25D01C08)
    0x00000000
    
    JESDTX_FIFO_FLAG_LANE1 (0x25D01C48)
    0x00000000
    
    JESDTX_FIFO_FLAG_LANE2 (0x25D01C88)
    0x00000000
    
    JESDTX_FIFO_FLAG_LANE3 (0x25D01CC8)
    0x00000000
    
    JESDTX_SYNC_STATE (0x25D00030)
    0x00000022
    
    JESDTX_SYSREF_ERR (0x25D02008)
    0x00000000
    
    JESDTX_ERR_CNT_LINK0 (0x25D01828)
    0x00000000
    
    JESDTX_ERR_CNT_LINK1 (0x25D01868)
    0x00000000
    
    JESDTX_FIRST_SYNC_REQ (0x25D00034)
    0x00000011

    But, When trying to receive a signal, I get a strange result (and its consistence):

    Is this problem familiar to you?

    Best regards,

    Eran.

  • Eran,

    Did you get a chance to check the output of the DAC on spectrum analyzer?

    This is to make sure the input signal to ADC is good.

    Thanks and Regards,

    Michelle

  • Michelle,

    Yes, I see a good signal on the spectrum.


    Best regards,

    Eran.

  • Eran,

    Since the JESD is good and you have valid signal as input, the possible problem would be 

    1. ADC NCO setting (make sure you set both input clock (2949.12) and NCO value to it)

    2. Web GUI display -- make sure GUI refresshes. Try removing cookie and also load different data pattern, check if tx/rx refreshes

    Another thing you can check is to see the dfe rx node capture. This is another way to see if NCO is correctly setup.

    Regards,

    Michelle