Reg SYSCLKOUT

Pradeep Naru

Other Parts Discussed in Thread: TMS320C6678

Hi,

In our design, DSP (TMS320C6678) SYSCLKOUT(single ended) has to be given to two FPGAs.(Virtex and kintex). Shall we need to use buffer(1:2)? or directly can be given?

Warms and Regards,

Pradeep N.

over 7 years ago

0 Raja over 7 years ago

TI__Guru* 81335 points

Hi Pradeep,

Please follow the keystone schematic checklist for clock termination,

Thank you.

0 Senthilkumar Srinivasan over 7 years ago

TI__Mastermind 43660 points

Pradeep,

It would be good practice to use buffer.

Regards,
Senthil

0 Pradeep Naru over 7 years ago in reply to Senthilkumar Srinivasan

Intellectual 300 points

Thank you senthilkumar

rgds,

Pradeep N.

Processors

Processors forum

Reg SYSCLKOUT