Hi all,
I used this gel to configure 66AK2H140844.xtcievmk2x_DDR.gelAnd the GEL output was below
C66xx_0: GEL Output: Connecting Target... C66xx_0: GEL Output: TCI6638K2K GEL file Ver is 1.60000002 C66xx_0: GEL Output: Detected PLL bypass enabled: SECCTL[BYPASS] = 0x00800000 C66xx_0: GEL Output: (2a) MAINPLLCTL1 = 0x00000040 C66xx_0: GEL Output: (2b) PLLCTL = 0x00000048 C66xx_0: GEL Output: (2c) PLLCTL = 0x00000048 C66xx_0: GEL Output: (2d) Delay... C66xx_0: GEL Output: (2e) SECCTL = 0x00810000 C66xx_0: GEL Output: (2f) PLLCTL = 0x0000004A C66xx_0: GEL Output: (2g) Delay... C66xx_0: GEL Output: (2h) PLLCTL = 0x00000048 C66xx_0: GEL Output: (4)PLLM[PLLM] = 0x0000000F C66xx_0: GEL Output: MAINPLLCTL0 = 0x05000000 C66xx_0: GEL Output: (5) MAINPLLCTL0 = 0x07000000 C66xx_0: GEL Output: (5) MAINPLLCTL1 = 0x00000040 C66xx_0: GEL Output: (6) MAINPLLCTL0 = 0x07000000 C66xx_0: GEL Output: (7) SECCTL = 0x00890000 C66xx_0: GEL Output: (8a) Delay... C66xx_0: GEL Output: PLL1_DIV3 = 0x00008002 C66xx_0: GEL Output: PLL1_DIV4 = 0x00008004 C66xx_0: GEL Output: PLL1_DIV7 = 0x00000000 C66xx_0: GEL Output: (8d/e) Delay... C66xx_0: GEL Output: (10) Delay... C66xx_0: GEL Output: (12) Delay... C66xx_0: GEL Output: (13) SECCTL = 0x00090000 C66xx_0: GEL Output: (Delay... C66xx_0: GEL Output: (Delay... C66xx_0: GEL Output: (14) PLLCTL = 0x00000041 C66xx_0: GEL Output: PLL has been configured (CLKIN * PLLM / PLLD / PLLOD = PLLOUT): C66xx_0: GEL Output: PLL has been configured (122.879997 MHz * 16 / 1 / 2 = 983.039978 MHz) C66xx_0: GEL Output: Power on all PSC modules and DSP domains... C66xx_0: GEL Output: Power on all PSC modules and DSP domains... Done. C66xx_0: GEL Output: WARNING: SYSCLK is the input to the PA PLL. C66xx_0: GEL Output: Completed PA PLL Setup C66xx_0: GEL Output: PAPLLCTL0 - before: 0x0x098804C0 after: 0x0x09080500 C66xx_0: GEL Output: PAPLLCTL1 - before: 0x0x00000040 after: 0x0x00002040 C66xx_0: GEL Output: DDR begin C66xx_0: GEL Output: XMC setup complete. C66xx_0: GEL Output: DDR3 PLL (PLL2) Setup ... C66xx_0: GEL Output: DDR3 PLL Setup complete, DDR3A clock now running at 666 MHz. C66xx_0: GEL Output: DDR3A initialization complete C66xx_0: GEL Output: DDR3 PLL (PLL2) Setup ... C66xx_0: GEL Output: DDR3 PLL Setup complete, DDR3B clock now running at 533MHz. C66xx_0: GEL Output: DDR3B initialization complete C66xx_0: GEL Output: DDR done
Then I tried to read the memory@0x80000000 or 0x60000000, it showed me like this
Then I checked the DDR3A/B PHY register.
The value of PGSR0@DDR3A was 0xB1E001FF
The value of PGSR0@DDR3B was 0xB0E000FF
E meant that the Writing Leveling Adjustment Error, DQS Gate Training Error and Write Leveling Error.
I supposed that these errors was the reason why I couldn't access to the memory@0x80000000 and 0x60000000.
Then I tried to adjust the parameters of DDR3 controller or PHY.
When I debugged the C6678 ever, I had downloaded one excel and filled the PCB routing length and then calculated the parameters I should configure the DDR3 controller and PHY. It looks like this.
But in the doc Keystone II DDR3 Initialization, it told me to download this ttp://www.ti.com/lit/zip/sprabx7 to calculate the parameters.
But in this excel K2 DDR3 Register Calc v1p60.xlsx, I can't the places I should fill in the PCB routing length values. So it confuse me very much.
Could anyone tell me how to debug to make sure the 66AK2H14's DDR3 leveling is OK?
Regards,
Feng