Interrupt redefined error at 2nd run

Anil Swamy

Intellectual 750 points

Other Parts Discussed in Thread: SYSBIOS

Hi,

I am running VCP2 example code on TI6638 K2K EVM hardware,

Following error are seen at second run

· for the first run VCP2 running fine interrupt are generated and we getting expected results.

· at the time of second run we are getting an error message at interrupt is already used.

“ti.sysbios.family.c64p.Hwi: line 192: E_alreadyDefined: Hwi already defined: intr# 6 xdc.runtime.Error.raise: terminating execution”

· Interrupts are cleared after the ISR is called and also EDMA interrupts are cleared, still we are getting an error message interrupt already used,

Code flow.

· Initial power on done for all the 8VCP2 instance at core ‘0’. Inside vcp2Init function

· Initialization of EDMA3 is done for all the core ‘0’ to ‘7’ inside edma3ModuleInit function.

· Configuration of VCP2 parameter done inside setupVcpTputEdma3 function.

· Configuration of interrupts and channels done inside the edma3MultChnlEnable function, four interrupts are configured, Interrupt configuration of VCP2 transmit XEVT0 number: 29 and Interrupt configuration of VCP2 receive 0_REVT0 number: 28 and also interrupt configuration of VCP2_RCV_OPPARAM_TCC_VCP0 and VCP2_XMT_IPCONFIG_TCC_VCP0 are done.

· Interrupts are enabled inside the Setup_Interrupt function, Interrupt vector ‘6’ we are using. ‘CSL_INTC_VECTID_6’ and also mapping of system interrupts to proper output interrupts (channels) enabling is done.

· Due to this error not able to proceed further. Please provide inputs if i am missing any configuration or something wrong in interrupt setup, waiting for reply.

· Code snippet below for enabling the channel and EDMA interrupts.

void edma3MultChnlEnable(Uint32 edmaRegionNum)

{

/* Interrupt Event*/

regionIntr.region = edmaRegionNum;

regionIntr.intrh= 1 << (VCP2_XMT_TCC(/*coreNum1*/edmaRegionNum)-0x20);

regionIntr.intr= 0;

CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_INTR_ENABLE,&regionIntr);

CSL_edma3HwChannelControl(hEdma3VcpXevt,CSL_EDMA3_CMD_CHANNEL_ENABLE,NULL);

regionIntr.region = edmaRegionNum;

regionIntr.intrh |= 1 << (VCP2_RCV_TCC(/*coreNum1*/edmaRegionNum)-0x20);

regionIntr.intr=0;

CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_INTR_ENABLE,&regionIntr);

CSL_edma3HwChannelControl(hEdma3VcpRevt,CSL_EDMA3_CMD_CHANNEL_ENABLE,NULL);

regionIntr.region = edmaRegionNum;

//regionIntr.intrh |= 1 << VCP2_RCV_OPPARAM_TCC(coreNum1);

regionIntr.intr |=1 << (VCP2_RCV_OPPARAM_TCC(/*coreNum1*/edmaRegionNum));

CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_INTR_ENABLE,&regionIntr);

CSL_edma3HwChannelControl(hEdma3VcpRevt,CSL_EDMA3_CMD_CHANNEL_ENABLE,NULL);

regionIntr.region = edmaRegionNum;

//regionIntr.intrh |= 1 << VCP2_XMT_IPCONFIG_TCC(coreNum1);

regionIntr.intr |= 1 << (VCP2_XMT_IPCONFIG_TCC(/*coreNum1*/edmaRegionNum));

CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_INTR_ENABLE,&regionIntr);

CSL_edma3HwChannelControl(hEdma3VcpRevt,CSL_EDMA3_CMD_CHANNEL_ENABLE,NULL);

}

· Code snippet interrupts is enabled

hCpintc = CSL_CPINTC_open(1); // handle for INTC0

CSL_CPINTC_disableAllHostInterrupt(hCpintc);

CSL_CPINTC_setNestingMode(hCpintc, CPINTC_NO_NESTING);

CSL_CPINTC_mapSystemIntrToChannel (hCpintc, CSL_CIC0_I2C_1_INT , 8);

CSL_CPINTC_clearSysInterrupt (hCpintc, CSL_CIC0_I2C_1_INT );

CSL_CPINTC_enableSysInterrupt (hCpintc, CSL_CIC0_I2C_1_INT );

Hwi_Params hwiParams;

Hwi_disable();

Hwi_disableInterrupt(CSL_INTC_VECTID_6);

Hwi_Params_init(&hwiParams);

hwiParams.enableInt = FALSE;

hwiParams.eventId = CSL_C66X_COREPAC_CIC_OUT8_PLUS_16_MUL_N ;

Hwi_create (CSL_INTC_VECTID_6, (ti_sysbios_interfaces_IHwi_FuncPtr) EDMA_ISR, &hwiParams, NULL);

Hwi_clearInterrupt (CSL_INTC_VECTID_6);

Thanks & regards,

Anil Kumar

If I am missing any configuration please provide input

over 7 years ago

0 Raja over 7 years ago

TI__Guru* 81335 points

CSL_CPINTC_disableAllHostInterrupt(hCpintc);
CSL_CPINTC_setNestingMode(hCpintc, CPINTC_NO_NESTING);
CSL_CPINTC_mapSystemIntrToChannel (hCpintc, CSL_CIC0_I2C_1_INT , 8);
CSL_CPINTC_clearSysInterrupt (hCpintc, CSL_CIC0_I2C_1_INT );
CSL_CPINTC_enableSysInterrupt (hCpintc, CSL_CIC0_I2C_1_INT );

Hwi_Params hwiParams;
Hwi_disable();

Hwi_disableInterrupt(CSL_INTC_VECTID_6);
Hwi_Params_init(&hwiParams);
hwiParams.enableInt = FALSE;
hwiParams.eventId = CSL_C66X_COREPAC_CIC_OUT8_PLUS_16_MUL_N ;
Hwi_create (CSL_INTC_VECTID_6, (ti_sysbios_interfaces_IHwi_FuncPtr) EDMA_ISR, &hwiParams, NULL);
Hwi_clearInterrupt (CSL_INTC_VECTID_6);

What is the value of CSL_CIC0_I2C_1_INT, CSL_C66X_COREPAC_CIC_OUT8_PLUS_16_MUL_N ?

The host interrupt is not enabled. There seems to be issue with interrupt configuration, please refer the attached example to correct the sequence.

CSL_CPINTC_enableSysInterrupt (hCpintc, CSL_CIC0_I2C_1_INT );


/* Enable Host interrupt 3 */
CSL_CPINTC_enableHostInterrupt (hCpintc, CSL_C66X_COREPAC_CIC_OUT8_PLUS_16_MUL_N);

/* Enable all host interrupts also. */
CSL_CPINTC_enableAllHostInterrupt(hCpintc);

hyplnkIsr.c

/*
 *
 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ 
 * 
 * 
 *  Redistribution and use in source and binary forms, with or without 
 *  modification, are permitted provided that the following conditions 
 *  are met:
 *
 *    Redistributions of source code must retain the above copyright 
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the 
 *    documentation and/or other materials provided with the   
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
*/

/*  
 *  This file contains the interrupt service routines and the
 *  code to install them.
 */
#include <ti/csl/cslr_device.h>
#include <ti/csl/csl_cpIntcAux.h>
#include <ti/drv/hyplnk/hyplnk.h>
#include <csl_intc.h>
#include <csl_intcAux.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include "hyplnkIsr.h"
#include "hyplnkPlatCfg.h"
#include <c6x.h>


CSL_IntcEventHandlerRecord  hyplnkExampleEvtHdlrRecord[2];
CSL_IntcObj                 hyplnkExampleIntcObj;
CSL_IntcHandle              hyplnkExampleIntcHnd;
CSL_IntcContext             hyplnkExampleIntcContext;

volatile int hyplnkExampleFatalReason = -1;
/*****************************************************************************
 * Trap/infinite loop entered when a fatal error is detected in the ISR
 * printf() and exit() are not reliable from an ISR.
 ****************************************************************************/
void hyplnkExampleFatal (int reason) {
  hyplnkExampleFatalReason = reason;
  while(1);
}

/*****************************************************************************
 * This attempts to pretty print the fatal error.  No guarantees it will
 * work from ISR context.
 ****************************************************************************/
void hyplnkExampleCheckOneStat (hyplnkLocation_e  location,
                                const char       *name,
                                int               noWarn);

/*****************************************************************************
 * Hyperlink ISR handler
 ****************************************************************************/
void hyplnkExampleIsr (void *eventId)
{
  hyplnkRegisters_t       regs;
  hyplnkIntStatusClrReg_t intStatusClr;
  hyplnkIntPendSetReg_t   intPendSet;
  Hyplnk_Handle           handle = NULL;
  uint32_t                remainingInterrupts;
  CSL_CPINTC_Handle       cpintcHnd;

  cpintcHnd = CSL_CPINTC_open (0);
  if (! cpintcHnd) {
    hyplnkExampleFatal(0);
  }

  memset (&regs, 0, sizeof(regs));
  regs.intStatusClr = &intStatusClr;

  if (Hyplnk_open(0, &handle) != hyplnk_RET_OK) {
    hyplnkExampleFatal(1);
  }

  /* Figure out which interrupt it is */
  if (Hyplnk_readRegs (handle, hyplnk_LOCATION_LOCAL, &regs) != hyplnk_RET_OK) {
    hyplnkExampleFatal(2);
  }

  /* Process the fatal error interrupt */
  remainingInterrupts = intStatusClr.intClr;
  if (remainingInterrupts & (1 << hyplnk_EXAMPLE_ISRNUM_FATAL)) {
    remainingInterrupts &= ~(1 << hyplnk_EXAMPLE_ISRNUM_FATAL);
    printf ("Fatal error detected\n");
    hyplnkExampleCheckOneStat (hyplnk_LOCATION_LOCAL, "fatal isr", 1);
    hyplnkExampleFatal(3);
  }

  /* Placeholder to process other interrupts that happened at the same time */
  if (remainingInterrupts) {
    printf ("Unknown interrupts: 0x%08x\n", remainingInterrupts);
  }

  /* Clear the interrupt */
  if (Hyplnk_writeRegs (handle, hyplnk_LOCATION_LOCAL, &regs) != hyplnk_RET_OK) {
    hyplnkExampleFatal(4);
  }

  /* Acknowledge CorePac interrupt */
  CSL_intcHwControl(hyplnkExampleIntcHnd, CSL_INTC_CMD_EVTCLEAR, NULL);
  /* Acknowledge cp intc interrupt */
  CSL_CPINTC_clearSysInterrupt (cpintcHnd, CSL_INTC0_VUSR_INT_O);

  /* Retrigger any remaining interrupts */
  intPendSet.intSet = 0;
  regs.intStatusClr = NULL;
  regs.intPendSet   = &intPendSet;
  if (Hyplnk_writeRegs (handle, hyplnk_LOCATION_LOCAL, &regs) != hyplnk_RET_OK) {
    hyplnkExampleFatal(4);
  }

  if (Hyplnk_close (&handle) != hyplnk_RET_OK) {
    hyplnkExampleFatal(5);
  }

}

/*****************************************************************************
 * Set up the INTC that is in the CorePac.  This works the same way on
 * any c64x or c66x
 ****************************************************************************/
static int hyplnkExampleInitCoreIntc (void)
{
  CSL_IntcGlobalEnableState   state;

  /* INTC module initialization */
  hyplnkExampleIntcContext.eventhandlerRecord = hyplnkExampleEvtHdlrRecord;
  hyplnkExampleIntcContext.numEvtEntries      = 2;
  if (CSL_intcInit (&hyplnkExampleIntcContext) != CSL_SOK) 
    return -1;

  /* Enable NMIs */
  if (CSL_intcGlobalNmiEnable () != CSL_SOK) 
    return -1;
 
  /* Enable global interrupts */
  if (CSL_intcGlobalEnable (&state) != CSL_SOK) 
    return -1;

  /* INTC has been initialized successfully. */
  return 0;
}

/*****************************************************************************
 * Set up the INTC that is at the chip level.  This varies over the various
 * c66x devices.
 ****************************************************************************/
static int hyplnkExampleInitChipIntc (void)
{
  CSL_CPINTC_Handle hnd;

  hnd = CSL_CPINTC_open (0);
  if (! hnd) {
    return -1;
  }
  /* Disable all host interrupts. */
  CSL_CPINTC_disableAllHostInterrupt(hnd);
    
  /* Configure no nesting support in the CPINTC Module. */
  CSL_CPINTC_setNestingMode (hnd, CPINTC_NO_NESTING);

  /* Clear CSL_INTC0_VUSR_INT_O */
  CSL_CPINTC_clearSysInterrupt (hnd, CSL_INTC0_VUSR_INT_O);
  /* Enable it */
  CSL_CPINTC_enableSysInterrupt (hnd, CSL_INTC0_VUSR_INT_O);
  CSL_CPINTC_mapSystemIntrToChannel (hnd, CSL_INTC0_VUSR_INT_O, hyplnk_EXAMPLE_INTC_OUTPUT);
  /* Do not need to use CSL_CPINTC_mapChannelToHostInterrupt because the mapping is static
   * such that channel and host interrupt are the same 
   */

  /* Enable it */
  CSL_CPINTC_enableHostInterrupt (hnd, hyplnk_EXAMPLE_INTC_OUTPUT);

  CSL_CPINTC_enableAllHostInterrupt(hnd);

  return 0;
}

/*****************************************************************************
 * Install the interrupt service routine
 ****************************************************************************/
int hyplnkExampleInitVec() 
{
  CSL_IntcParam vectId = hyplnk_EXAMPLE_COREPAC_VEC;
  Int16         eventId = hyplnk_EXAMPLE_COREPAC_INT_INPUT;

  hyplnkExampleIntcHnd = CSL_intcOpen (&hyplnkExampleIntcObj, eventId, &vectId, NULL);
  if (! hyplnkExampleIntcHnd) {
    return 0;
  }

  hyplnkExampleEvtHdlrRecord[0].handler = hyplnkExampleIsr;
  hyplnkExampleEvtHdlrRecord[0].arg     = (void *)eventId;
  CSL_intcPlugEventHandler(hyplnkExampleIntcHnd, hyplnkExampleEvtHdlrRecord);
  CSL_intcHwControl(hyplnkExampleIntcHnd, CSL_INTC_CMD_EVTCLEAR, NULL);
  CSL_intcHwControl(hyplnkExampleIntcHnd, CSL_INTC_CMD_EVTENABLE, NULL);
  return 0;
}

/*****************************************************************************
 * Set up an ISR handler for the hyperlink error event
 ****************************************************************************/
void hyplnkExampleInstallIsr (void)
{
  /* Setup up the core-specific INTC */
  if (hyplnkExampleInitCoreIntc()) {
    printf ("Failed to set up CorePac INTC\n");
    exit(1);
  }

  /* Connect hyperlink's common interrupt to a CorePac event */
  if (hyplnkExampleInitChipIntc()) {
    printf ("Failed to set up Chip INTC\n");
    exit(1);
  }

  /* Connect the CorePac event to a vector */
  if (hyplnkExampleInitVec()) {
    printf ("Failed to set up interrupt vector\n");
    exit(1);
  }
}

/* Nothing past this point */

0 Anil Swamy over 7 years ago in reply to Raja

Intellectual 750 points

Hi Raja,

Thanks a lot for your reply,

Value of SL_CIC0_I2C_1_INT = (0x000000EC), and CSL_C66X_COREPAC_CIC_OUT8_PLUS_16_MUL_N = (0x0000004A) and Host interrupt is enabled,

File is shared below, still i am getting the same error, interrupt redefined error or some time exception error.

Please provide some inputs. Waiting for your reply.

3441.vcp2_interrupt.c

/************************************************************************
*
*  SOURCE NAME: vcp2_interrupt.c
*
*************************************************************************
*
*  SOURCE FUNCTION: Header file for vcp2_interrupt.c
*
*
*  PROCEDURES IN THIS SOURCE FILE: Interrupt setup and handling
*  									functions for the VCP2
*
*

*********************************************************************/

#include <stdio.h>
#include <ti/csl/csl.h>
#include <ti/csl/csl_tsc.h>
#include <ti/csl/csl_types.h>
#include <ti/csl/csl_error.h>
#include <csl_intc.h>
#include <ti/csl/csl_edma3.h>
#include <ti/csl/csl_vcp2.h>
#include <ti/csl/csl_vcp2Aux.h>
#include <ti/csl/soc.h>
#include <ti/csl/csl_cpIntcAux.h>
#include <ti/csl/csl_device_interrupt.h>
#include <xdc/cfg/global.h>


/* BIOS includes */
#include <ti/sysbios/knl/Task.h>
#include <ti/sysbios/BIOS.h>
#include <ti/sysbios/knl/Semaphore.h>
#include <ti/sysbios/family/c64p/Hwi.h>
#include <ti/sysbios/family/c64p/EventCombiner.h>
#include <ti/sysbios/family/c66/tci66xx/CpIntc.h>

#include "val_util.h"
#include "vcp2_edma3.h"
#include "vcp2_testInit.h"

// Global variable declaration
CSL_IntcHandle              hIntcEdma;
CSL_IntcHandle              hIntcVcp;
CSL_IntcObj                 intcObjEdma;
CSL_IntcObj                 intcObjVcp;
CSL_CPINTC_Handle           hCpintc;
CSL_IntcEventHandlerRecord  eventHandler[2];
CSL_IntcGlobalEnableState   state;  //dummy var since not used to restore state later
CSL_Edma3CmdIntr            regionIntrQuerry;


CSL_CPINTCSystemInterrupt	sysIntr;

// External global variables

extern CSL_Edma3Handle hModule;
extern Semaphore_Handle SEM;

extern Uint32 decisions[4][1024];
extern VCP2_Params vcpParameters[20];

extern volatile Uint32 VcpError;
extern volatile Uint32 RxCount;

extern volatile Uint32 TxEdmaChannelBCount;
extern volatile Uint32 ChannelTXCount;
extern volatile Uint32 ChannelRXCount;

extern VCP2Handle hVcp2;
extern Uint32 coreNum1;

// Function declarations
interrupt void EDMA_ISR(void);
interrupt void VCP2_ISR(void);

//-------------------------------------------------------------
// Setup_Interrupt() - Performs setup for GEM INTC and CP_INTC
//-------------------------------------------------------------
void Setup_Interrupt()
{
    //---------------------------------
    // Setup GEM internal INTC
    //---------------------------------
	// printf("Star of Setup_Interrupt \n");
    // Declare variables
    /* Routing Iqn2 exception event thru INTC0 */


	  if(coreNum1 <= 3)
	  {
		hCpintc = CSL_CPINTC_open(0); // handle for INTC0
        CSL_CPINTC_disableAllHostInterrupt(hCpintc);
        CSL_CPINTC_setNestingMode(hCpintc, CPINTC_NO_NESTING);
        CSL_CPINTC_mapSystemIntrToChannel (hCpintc, CSL_CIC0_I2C_1_INT , 8); // assuming core0
        CSL_CPINTC_clearSysInterrupt (hCpintc, CSL_CIC0_I2C_1_INT );
        CSL_CPINTC_enableSysInterrupt (hCpintc, CSL_CIC0_I2C_1_INT );
	  }
	  else
	  {
		hCpintc = CSL_CPINTC_open(1); // handle for INTC0
		CSL_CPINTC_disableAllHostInterrupt(hCpintc);
		CSL_CPINTC_setNestingMode(hCpintc, CPINTC_NO_NESTING);
		CSL_CPINTC_mapSystemIntrToChannel (hCpintc, CSL_CIC1_I2C_1_INT , 8); // assuming core0
		CSL_CPINTC_clearSysInterrupt (hCpintc, CSL_CIC1_I2C_1_INT );
		CSL_CPINTC_enableSysInterrupt (hCpintc, CSL_CIC1_I2C_1_INT );
	  }
        Hwi_Params hwi1Params, hwi2Params;
        Hwi_disable();

        Hwi_disableInterrupt(CSL_INTC_VECTID_6);
        Hwi_disableInterrupt(CSL_INTC_VECTID_5);

        Hwi_Params_init(&hwi1Params);
        hwi1Params.enableInt = FALSE;
        hwi1Params.eventId =   CSL_C66X_COREPAC_CIC_OUT8_PLUS_16_MUL_N ;

		Hwi_Params_init(&hwi2Params);
		hwi2Params.enableInt = FALSE;
		hwi2Params.eventId =   CSL_C66X_COREPAC_CIC_OUT9_PLUS_16_MUL_N ;


        Hwi_create (CSL_INTC_VECTID_6, (ti_sysbios_interfaces_IHwi_FuncPtr) EDMA_ISR, &hwi1Params, NULL);
        Hwi_create (CSL_INTC_VECTID_5, (ti_sysbios_interfaces_IHwi_FuncPtr) VCP2_ISR, &hwi2Params, NULL);

        Hwi_clearInterrupt (CSL_INTC_VECTID_6);
        Hwi_clearInterrupt (CSL_INTC_VECTID_5);


#if 0

    CSL_IntcParam vectId1;
    CSL_IntcParam vectId2;
    CSL_IntcGlobalEnableState state;
    CSL_IntcContext intContext; 

    // Setup the global Interrupt
    intContext.numEvtEntries = 2;
    intContext.eventhandlerRecord = eventHandler; 

    CSL_intcInit(&intContext);

    // Enable NMIs
    CSL_intcGlobalNmiEnable();


    // Enable Global Interrupts
    CSL_intcGlobalEnable(&state);

    // Select interrupt vector IDs to use on DSP core
    vectId1 = CSL_INTC_VECTID_9;
    vectId2 = CSL_INTC_VECTID_10;

    // Map GEM input interrupt used for EDMA completion to vectId1  
    hIntcEdma = CSL_intcOpen(&intcObjEdma,
    		CSL_C66X_COREPAC_CIC_OUT8_PLUS_16_MUL_N,
            &vectId1,
            NULL);

    // Map GEM input interrupt used for VCP error to vectId2  
    hIntcVcp = CSL_intcOpen(&intcObjVcp,
    		CSL_C66X_COREPAC_CIC_OUT9_PLUS_16_MUL_N,
            &vectId2,
            NULL);

    // Hook the ISR's
    CSL_intcHookIsr(vectId1,&EDMA_ISR);
    CSL_intcHookIsr(vectId2,&VCP2_ISR);

    // Clear any pending interrupts
    CSL_intcHwControl(hIntcEdma,CSL_INTC_CMD_EVTCLEAR,NULL);
    CSL_intcHwControl(hIntcVcp,CSL_INTC_CMD_EVTCLEAR,NULL);

    // Enable the event and interrupt
     CSL_intcHwControl(hIntcEdma,CSL_INTC_CMD_EVTENABLE,NULL);
     CSL_intcHwControl(hIntcVcp,CSL_INTC_CMD_EVTENABLE,NULL);

#endif
    //----------------------------------------------------------
    // Setup CP_INTC
    //----------------------------------------------------------
    if(coreNum1 <= 3)
    {
    // Open a handle to CP_INTC instance 0
    hCpintc = CSL_CPINTC_open(CSL_CIC_0);
    if (hCpintc == 0)
		{
			printf ("Error: Unable to open CPINT instance 0\n");
			return;
		}
    }
    else
    {
    	hCpintc = CSL_CPINTC_open(CSL_CIC_1);
    	if (hCpintc == 0)
    	{
        printf ("Error: Unable to open CPINT instance 0\n");
        return;       
    	}
    }

    // Map EDMA completion and VCP error system interrupts to proper output interrupts (channels) and enable
    if (coreNum1 == 0) {
        CSL_CPINTC_mapSystemIntrToChannel (hCpintc, CSL_CIC1_EDMACC_3_TC_0_INT, (16 * coreNum1) + 8);
        CSL_CPINTC_mapSystemIntrToChannel (hCpintc, CSL_CIC1_VCP_0_INT0,          (16 * coreNum1) + 9);
        CSL_CPINTC_enableSysInterrupt (hCpintc, CSL_CIC1_EDMACC_3_TC_0_INT);
        CSL_CPINTC_enableSysInterrupt (hCpintc, CSL_CIC1_VCP_0_INT0);
    } else if (coreNum1 == 1) {
        CSL_CPINTC_mapSystemIntrToChannel (hCpintc, CSL_CIC1_EDMACC_3_TC_1_INT, (16 * coreNum1) + 8);
        CSL_CPINTC_mapSystemIntrToChannel (hCpintc, CSL_CIC1_VCP_0_INT1,          (16 * coreNum1) + 9);
        CSL_CPINTC_enableSysInterrupt (hCpintc, CSL_CIC1_EDMACC_3_TC_1_INT);
        CSL_CPINTC_enableSysInterrupt (hCpintc, CSL_CIC1_VCP_0_INT1);
    } else if (coreNum1 == 2) {
        CSL_CPINTC_mapSystemIntrToChannel (hCpintc, CSL_CIC1_EDMACC_3_TC_2_INT, (16 * coreNum1) + 8);
        CSL_CPINTC_mapSystemIntrToChannel (hCpintc, CSL_CIC1_VCP_0_INT2,          (16 * coreNum1) + 9);
        CSL_CPINTC_enableSysInterrupt (hCpintc, CSL_CIC1_EDMACC_3_TC_2_INT);
        CSL_CPINTC_enableSysInterrupt (hCpintc, CSL_CIC1_VCP_0_INT2);
    } else if(coreNum1 == 3) {
        CSL_CPINTC_mapSystemIntrToChannel (hCpintc, CSL_CIC1_EDMACC_3_TC_3_INT, (16 * coreNum1) + 8);
        CSL_CPINTC_mapSystemIntrToChannel (hCpintc, CSL_CIC1_VCP_0_INT3,          (16 * coreNum1) + 9);
        CSL_CPINTC_enableSysInterrupt (hCpintc, CSL_CIC1_EDMACC_3_TC_3_INT);
        CSL_CPINTC_enableSysInterrupt (hCpintc, CSL_CIC1_VCP_0_INT3);
    }else if (coreNum1 == 4) {
	   CSL_CPINTC_mapSystemIntrToChannel (hCpintc, CSL_CIC1_EDMACC_3_TC_4_INT, (16 * (coreNum1-4)) + 8);
	   CSL_CPINTC_mapSystemIntrToChannel (hCpintc, CSL_CIC1_VCP_1_INT0,          (16 * (coreNum1-4)) + 9);
	   CSL_CPINTC_enableSysInterrupt (hCpintc, CSL_CIC1_EDMACC_3_TC_4_INT);
	   CSL_CPINTC_enableSysInterrupt (hCpintc, CSL_CIC1_VCP_1_INT0 );
    } else if (coreNum1 == 5) {
	   CSL_CPINTC_mapSystemIntrToChannel (hCpintc, CSL_CIC1_EDMACC_3_TC_5_INT, (16 * (coreNum1-4)) + 8);
	   CSL_CPINTC_mapSystemIntrToChannel (hCpintc, CSL_CIC1_VCP_1_INT1,          (16 * (coreNum1-4)) + 9);
	   CSL_CPINTC_enableSysInterrupt (hCpintc, CSL_CIC1_EDMACC_3_TC_5_INT);
	   CSL_CPINTC_enableSysInterrupt (hCpintc, CSL_CIC1_VCP_1_INT1);
    } else if (coreNum1 == 6) {
	   CSL_CPINTC_mapSystemIntrToChannel (hCpintc, CSL_CIC1_EDMACC_3_TC_6_INT, (16 * (coreNum1-4)) + 8);
	   CSL_CPINTC_mapSystemIntrToChannel (hCpintc, CSL_CIC1_VCP_1_INT2,          (16 * (coreNum1-4)) + 9);
	   CSL_CPINTC_enableSysInterrupt (hCpintc, CSL_CIC1_EDMACC_3_TC_6_INT);
	   CSL_CPINTC_enableSysInterrupt (hCpintc, CSL_CIC1_VCP_1_INT2);
    } else { // coreNum11 == 3
	   CSL_CPINTC_mapSystemIntrToChannel (hCpintc, CSL_CIC1_EDMACC_3_TC_7_INT, (16 * (coreNum1-4)) + 8);
	   CSL_CPINTC_mapSystemIntrToChannel (hCpintc, CSL_CIC1_VCP_1_INT3,          (16 * (coreNum1-4)) + 9);
	   CSL_CPINTC_enableSysInterrupt (hCpintc, CSL_CIC1_EDMACC_3_TC_7_INT);
	   CSL_CPINTC_enableSysInterrupt (hCpintc, CSL_CIC1_VCP_1_INT3);
    }
    /*
    // Clear pending system interrupts
    if (CSL_CPINTC_isInterruptPending(hCpintc) == TRUE)
    {
    // Get the source of the interrupt
    sysIntr = CSL_CPINTC_getPendingInterrupt(hCpintc);

    // Clear the interrupt
    CSL_CPINTC_clearSysInterrupt(hCpintc, sysIntr);
    }*/


    if(coreNum1 <= 3)
    {

    	// Enable output (host) interrupts to GEM
    	CSL_CPINTC_enableHostInterrupt (hCpintc, (16 * coreNum1) + 8);
    	CSL_CPINTC_enableHostInterrupt (hCpintc, (16 * coreNum1) + 9);
    	// Enable global host interrupt enable
    	CSL_CPINTC_enableAllHostInterrupt(hCpintc);

    }
    else
    {
		CSL_CPINTC_enableHostInterrupt (hCpintc, (16 * (coreNum1 -4)) + 8);
		CSL_CPINTC_enableHostInterrupt (hCpintc, (16 * (coreNum1 - 4)) + 9);
		// Enable global host interrupt enable
		CSL_CPINTC_enableAllHostInterrupt(hCpintc);

   	 }

    Hwi_enableInterrupt (CSL_INTC_VECTID_6);
	Hwi_enableInterrupt (CSL_INTC_VECTID_5);

	Hwi_enable ();
}


/*************************************************************************\
 *                    EDMA ISR
 \*************************************************************************/
interrupt void EDMA_ISR(void)
{

//	printf("Start of the EDMA_ISR \n");

    CSL_CPINTC_clearSysInterrupt(hCpintc, CSL_CIC1_EDMACC_3_TC_0_INT+coreNum1);
    CSL_intcHwControl(hIntcEdma,CSL_INTC_CMD_EVTCLEAR,NULL);

    regionIntrQuerry.region = coreNum1; // CSL_EDMA3_REGION_1;
    regionIntrQuerry.intrh = 0xffffffff;
    regionIntrQuerry.intr =0xffffffff;

    /* Read EDMA IPR */
    CSL_edma3GetHwStatus(hModule,CSL_EDMA3_QUERY_INTRPEND,&regionIntrQuerry); 
    /* Clear EDMA IPR */
    CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_INTRPEND_CLEAR,&regionIntrQuerry);


    VAL_TRACE(0xAAAA0000);
    do
    {
        /* Sample Timer Value after O/P Parameter Transfer is over */
        if(regionIntrQuerry.intr & (1 << VCP2_RCV_OPPARAM_TCC(coreNum1)))
        {

            ChannelRXCount++;
            VAL_TRACE(0xA0000003);
        }

        /* Sample Timer Value after I/P Parameter configuration is over */

        if(regionIntrQuerry.intr & (1 << VCP2_XMT_IPCONFIG_TCC(coreNum1)))
        {
            /* Populate the Time for Input Parameter XMT completion of Channel"i"*/
             VAL_TRACE(0xA0000004);
        }

        /* Start VCP BM Transfer */
        if(regionIntrQuerry.intrh & (1 << VCP2_XMT_TCC(coreNum1)-0x20))
        {

			ChannelTXCount++;
			VAL_TRACE(ChannelTXCount);
			VAL_TRACE(0xA0000005);
        }

        /* Start VCP Read for decisions */
        if(regionIntrQuerry.intr & (1 << VCP2_RCV_TCC(coreNum1)-0x20))
        {
            /* Populate the Time for RCV completion of Channel "i" */
            VAL_TRACE(0xA0000007);
            VAL_TRACE(ChannelRXCount);   

        }

        CSL_edma3GetHwStatus(hModule,CSL_EDMA3_QUERY_INTRPEND,&regionIntrQuerry); 
        CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_INTRPEND_CLEAR,&regionIntrQuerry);
   }while ((regionIntrQuerry.intr !=0)  & (regionIntrQuerry.intrh !=0));

    /* Set Interrupt EVAL */
 /*     regionIntrQuerry.region = coreNum1;
     CSL_edma3HwControl(hModule, CSL_EDMA3_CMD_INTR_EVAL,&regionIntrQuerry.region); */

   // Hwi_clearInterrupt (CSL_INTC_VECTID_6);
    CSL_CPINTC_clearSysInterrupt(hCpintc, sysIntr);

#if 1

    CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_DMAREGION_DISABLE,&regionIntrQuerry);
    CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_INTRPEND_CLEAR,&regionIntrQuerry);
    CSL_edma3HwControl(hModule, CSL_EDMA3_CMD_INTR_DISABLE, &regionIntrQuerry);
#endif

  //  Semaphore_post(SEM_VCP2Complete);
}


/*************************************************************************\
 *                    VCP2 ISR
 \*************************************************************************/
interrupt void VCP2_ISR(void)
{

    CSL_CPINTC_clearSysInterrupt(hCpintc, /*CSL_CIC0_VCP_0_INT0 */CSL_CIC1_VCP_0_INT0+coreNum1);
    CSL_intcHwControl(hIntcVcp,CSL_INTC_CMD_EVTCLEAR,NULL);
    VAL_TRACE(0xAAAA1100);

    // Read the Status Register
    VAL_TRACE(hVcp2->cfgregs->VCPSTAT0);
    VAL_TRACE(hVcp2->cfgregs->VCPSTAT1);

    // Read the VCP2 Error Register and set the status accordingly
    VAL_TRACE(hVcp2->cfgregs->VCPERR);
    hVcp2->cfgregs->VCPERR = 0;

    // Increment VCP error counter
    VAL_TRACE(0xAAAA11FF);
    VcpError++;

}


/******************************************************************************\
 * End of vcp2_interrupt.c
\******************************************************************************/

Thanks & regards,.

Anil Kumar

0 Raja over 7 years ago in reply to Anil Swamy

TI__Guru* 81335 points

Please refer below thread for interrupt related resources. Please check if that helps.

e2e.ti.com/.../538982

Thanks.

Processors

Processors forum

Interrupt redefined error at 2nd run