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How to Configure EDMA3 to be Triggered with Timer for K2H

Other Parts Discussed in Thread: 66AK2H06

I used 66AK2H06 and want to trigger the EDMA3 with timer output.

I found the following "CSL_EDMACC_1_TIMER_8_INTL". I think it means the timer 8 output low to trigger EDMACC1 event, right?

Where is he function to call this value, or to use this parameter?

//#define CSL_EDMACC_1_TIMER_8_INTL (0x00000016) in csl_device_interrupt.h

And channelNum =1 in the following program, what is the channelNum means?

/* Channel Open Global */
chAttr.regionNum = CSL_EDMA3_REGION_GLOBAL;
chAttr.chaNum = channelNum;

hChannel = CSL_edma3ChannelOpen(&chObj, instNum, &chAttr, &status);

What is the "1" means in the function pramameters?

/* Map the DMA Channel to the appropriate PARAM Block. */
CSL_edma3HwChannelSetupParam(hChannel, 1) ;

/* Obtain a handle to parameter set */
hParamBlock1 = CSL_edma3GetParamHandle(hChannel, 1, &status);

Thanks,

Wei Cao

  • Hi Wei Cao,

    Moved this thread over Keystone forum for appropriate response. Thank you.
  • I've notified the Edma experts. Their feedback will be posted directly here.

    Best Regards,
    Yordan
  • Hi Yordan,

    I want to use EDMA3 module and configure it for my DSP application for K2K device.
    Still not got any reply here from your EDMA experts.

    Regards,
    Hemanth, P
  • It seems to me that multiple customers posted on this thread.  Multiple customers may have different levels of experiences, so I will try to walk you through the process and I apologize if I go too slow.

    Step 1 -The first step should be reading the EDMA FAQ - ( http://processors.wiki.ti.com/index.php/EDMA_FAQ_for_KeystoneI/II_devices ) and make sure that you understand how the EDMA is working.

    Step 2 -  Next try to build a simple EDMA code that moves data from one buffer to a second buffer. Make sure that this work.

    Step 3 -Next step is to decide if you use BIOS to define timer, or using hardware timer directly (using csl functions to configure the timer)

    Step 4 -Next understand what event is generated by the timer and how to map this event into EDMA controller.

    Step 5 - Last combine the timer code with the EDMA code of step 2

    Please post where are you in the sequence and what difficulties you encounter and we will go from there.

    To illustrate how to use EDMA to move data from one location to another I attach a bare metal project.  Bare Metal means that the code does not use any standard drivers so you can see exactly what needs to be configured.  This is my personal project so no explicit or implicit guarantees is given, and the purpose is only to look at the source code.  In order to build the project and run it, the user may have to modify some parameters.

    EDMA examples that use EDMA drivers are part of the release. You can use one of them for step 2.

    Waiting to get an update post from you

    Ran   /cfs-file/__key/communityserver-discussions-components-files/791/6835.edmaBareMetal2.zip

  • Thank you very much Ran.

    I briefly read the links and still not get the answer. My question is how to use CSL API to configure the timer event to DMA3 channel.

    From my understand, there are 64 peripherals events related to the DMA.

    #define CSL_EDMACC_1_TIMER_8_INTL (0x00000016) //in csl_device_interript.h; is this timer 8 low output to trigger EDMAC 1 transfer?

    Can I use chaNum = CSL_EDMACC_1_TIMER_8_INTL for the following CSL_Edma3ChannelAttr configuration?

    typedef struct {

        /** Region Number */  

       Int regionNum;

       /** Channel number */                            

       Int chaNum;                                

    } CSL_Edma3ChannelAttr;

    Thank you very much.

    Wei

  • OK, I think that I understand what you ask

    In the User Guide (SPRS866) section 6.4.4, the end of the first paragraph it says that the the association of each synchronization event and DMA channel is fixed and cannot be reprogrammed.

    The following tables shows 64 events, each sets up an event for the correspondent channel. So table 6-34 shows what sets up the channels in EDMA controller 0, 6-35 for EDMA controller 1 and so on.

    Let's look at the first EDMA controller (6-34): The first 8 channels' events are connected directly to 8 interrupts from timers (more about it in a second). The next 8 events are connected to the output of the third Central Interrupt Controller (CIC2) - starting with output 66 to output 73. Thus mapping ANY input event of CIC2 to output (say) 66 will generate an event for channel 8, and so on.  You got the idea.

    A reminder, the Timers are 64-bit timers that can be configured as 2 32-bit timer, so each timer has two output events high and low.

    So, if you set timer 8 (say) to send an event when the timer expires, you expect to see channel 0 or channel 1 (depends if this is high or low) starts.  To debug it, I suggest looking at the ER register of the EDMA that you are interested in. To see it, disable the event in EER register, let the timer expires and verify that you see the right bit in register ER.  Note, register ER and ERH and registers EER and EERH are described in table 4-1 on page 91 of SPRUGS - EDMA3 User Guide.  Leave the shadow registers in the default state, namely, the global registers set is used and not the shadow registers.

    Report your observations at this point and we will see how to continue.

    Regards

    Ran

  • Thank you very much Ran. Very clear explanation!

    So I can use the following to configure, right?

    chAttr.regionNum = CSL_EDMA3_REGION_GLOBAL

    chAttr.chaNum = CSL_EDMACC_1_TIMER_8_INTL

    CSL_edma3ChannelOpen(&chObj, instNum, &chAttr, &status)

    Another piece of pulse for:

    CSL_CPINTC_mapSystemIntrToChannel (hnd, sysIntrpt, hostIntrpt)

    sysIntrpt is clear, in the csl_device_interrupt.h

    #define CSL_CIC0_EDMACC_1_GINT (0x00000006)

    sysIntrpt = CSL_CIC0_EDMACC_1_GINT

    However, the hostintrpt did not find correspondent *.h file.

    e.g.

    eventID is also clear in he csl_device_interrupt.h

    #define CSL_C66X_COREPAC_CIC_OUT32 (0x00000028)

    will connected to

    hostintrpt = 32?

    Where this 32 comes from, any *.h file specify it?

    Thank you very much again.

    Wei

  • If I remember correctly, host interrupt (sometimes they call it channel interrupt, I think) is the output pin. So CSL_CPINTC_mapSystemIntrToChannel (hnd, sysIntrpt, hostIntrpt) connects the sysIntrpt = the input even to the output line hostIntrpt

    My suggestion is to draw the connection on paper, and give the event numbers for each of the block. This will help you to configure whatever you want. Then look at the constants in the API and verify that the values are what you want (the correct EDMA channel number, the correct CIC2 output event line, the correct mapping of the timer to the CIC2 event line. The enable of the channel in the EER and EERH register, and then try your code.

    Now I am sure that I forgot some enabling. So if the EDMA does not run properly, start debugging the code using CCS. First verify that the timer send an event to the input side of CIC2 (find the register that latch the event), then look if the output line has the event (find the register that shows the output line and see the correct bit turns into 1). then look if the signal arrived to the ER register, then enable the EER and see if the edma is working. Somewhere along the chain you will find what we miss.

    I am sure you can debug your code. If a value is missing, you an immediate value in your code and do #define after the code is running correctly.
    And you are right, the 32 value must come from some #define. It does not have to be include file, it can be in the source code, so you can chase it, or you can just plug that correct numerical value

    Best regards

    Ran
  • Sorry I just found ER changed, but not trigger the transfer.
    CSL_edma3Init(&context) ;
    hModule = CSL_edma3Open(&edmaObj, edmaInst, NULL, &status);
    chAttr.regionNum = CSL_EDMA3_REGION_GLOBAL;//CSL_EDMA3_REGION_0;
    chAttr.chaNum = channelNum;
    hChannel = CSL_edma3ChannelOpen(&chObj, edmaInst, &chAttr, &status);
    CSL_edma3HwChannelSetupParam(hChannel, 1) ;
    hParamBlock1 = CSL_edma3GetParamHandle(hChannel, 1, &status);
    CSL_edma3ParamSetup(hParamBlock1,&myParamSetup);
    CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_INTR_ENABLE,&regionIntr);

    what I missed?
    Thank you very much,
    wei
  • So the ER bit is set but the EDMA does not start, right?

    What do you think can be the problem?  What do you need to configure in  order for the EDMA to start?

    Check to see the status of the EER register. Is the channel enabled?  if no, what instruction should enable the channel?


    How would you know if the EDMA worked or not? (I assume it does not work now,  but if you enable the channel, how would you know if it worked?)

    Look again at the bare metal example that I attached to this posting earlier. Go step by step and verify that all the steps in the bare metal example are done by your code.  I am sure that you will find what is missing.

    Regards

    Ran

  • Ran,
    I got the timer triggered the EDMA and core0 ISR worked. Thank you very much.
    Now I have other question:
    I need one DMA triggered by the timer from DDR3 to L2, another QDMA triggered by the core0 in the ISR.
    I set the timer triggered EDMA output by global, and set the QDMA output by region 1 in the same EDMA module 0.
    I found when set the global for the timer triggered DMA, the region register is -1, but when set the QDMA for region 1, the first channel region changed to 1 from -1. I used the same module handler but with different channel handlers.
    How many channels can be independently set in one module?
    Can we assign the EDMA output, global, 1 to 7 to each channel? and how?
    Thank you very much,
    Wei
  • I am not sure if I understand your question, so if I answer the wrong question please post your question again

    1. Each EDMA controller (CC) has 64 DMA channels and 8 QDMA channels.
    2. Channel can send out an event upon completion or intermediate status. The event is recorded in the IPR/IPRH registers (each one has 32 bit, so 64 bits all together)
    3. The TCC field of the OPT word of the PaRam determines the bit that is set upon completion (or after intermediate). the TCC has 6 bits so it can address up to 64 locations, and the IPR/IPRH have only 64 bits anyhow.
    4. Thus there is a problem if one wants to use all 64 DMA channels and 8 QDMA channels
    5. The introduction of the Shadow registers (The region) solves this issue. Now the user can attach the DMA channels to the global set of shadow registers, and the QDMA channels to a different shadow registers set, say to region 1
    6. One can guess that what you see id the result of the software separate DMA from QDMA channels.
    7. My suggestion to you is to keep the channel as described above, namely, all DMA are associated with Global set, all QDMA are associated with Shadow Register set 1 - region 1.
    8. When you channel the EDMA interrupt to either a host or chain channels, make sure that you take the Region into considerations

    Does it answer your question? as usual please close the thread. If you have more questions please open a new thread

    Ran
  • Ran,
    I got another question now.
    I can DMA from _src1 to dst1, but no thing happened (no transfer) when _src2 to dst2, no error.
    What is the trick?
    Thank you very much,
    Wei

    DMA_src1: o = 0x80000000 l = 0x100
    DMA_dst1: o = 0x10800000 l = 0x100
    DMA_src2: o = 0x10800200 l = 0x100
    DMA_dst2: o = 0x80000200 l = 0x100
  • Please post the question in a new thread with all the details

    Best regards

    Ran