• State Resolved
  • Locked Locked
  • Replies 5 replies
  • Answers 2 answers
  • Subscribers 102 subscribers
  • Views 704 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Query on MPAX feature in TI 6636 K2H platform.

k j
Prodigy 40 points

We are evaluating the MPAX feature in TI 6636 K2H platform. We have gone through the manuals in this area and

have a basic understanding of the same.

 

Question 1)

We  are interested in knowing if it is possible to implement an equivalent MPAX feature

completely in software?

If yes, what are the pros and cons and if no, can you please let us know the reason.

 

Question 2)

 

We would also be interested in understanding what run time overhead we would incur and will it potentially have an

impact on the application, because of including the MPAX feature (Hardware memory protection).

  • 0
    TI__Guru* 81335 points
    We have notified our experts to comment. They will get back to you. Thank you for your patience.
  • 0 in reply to Raja
    TI__Genius 12805 points

    Question 1)

    We  are interested in knowing if it is possible to implement an equivalent MPAX feature

    completely in software?

    If yes, what are the pros and cons and if no, can you please let us know the reason.

    >>>>>>>[rk] The MPAX registers do logical to physical translation.  You cannot get more than 32-bit addressing (limiting to 2GB external memory). Other than this, you can develop a software MMU for the DSP that will do page allocation and trash collection. It will require changing your code so read and write via the software MMU, but why? what advantages it will give you?  I see only disadvantages. You will not gain any cycles since the IO operations go via the MPAX anyhow.

    If you are interested in memory protection, not necessary the translation, check the various MPU in the system.  Depends what memory you want to protect, you may have a MPU that does it. Again, I ask why?

    On the ARM the equivalent of the MPAX is the MMU. You can disable the Large Memory Extension mode and have logical addressing translated directly to physical addressing.

    The SES and the SMS MPAX are even more interesting. Here you can speed up the memory access if you disable the ARM  coherency feature.  Is this what you are looking for?

    To summarize: I see no advantage in software MPAX, and it can only support part of the MPAX features. My suggestion - do not do it.

     

    Question 2)

     

    We would also be interested in understanding what run time overhead we would incur and will it potentially have an

    impact on the application, because of including the MPAX feature (Hardware memory protection).

    >>>>[RK}  Again, the hardware IO goes through the MPAX so I do not think any overhead advantage will be gained.  The only area where you can gain performances is if you disable the ARM coherency for IO traffic.  For example, if you get data into the DDR that ONLY DSP needs, you do not need to check the ARM cache.   This may save you time.  Look at the multi-core shared memory document http://www.ti.com/lit/ug/spruhj6/spruhj6.pdf for more details

    Ran

  • 0 in reply to ran35366
    Prodigy 40 points
    Thanks Ran, for the elaborate answer. We appreciate it.

    We are currently looking at DSP only. So, we request you to provide info pertaining to DSP. We do not have much understanding of the ARM architecture.Also, we are currently looking at the MPPA part of MPAX. We are yet to get into the "AX" part of MPAX.

    Query 1)
    If we have to also do Address Extension part, what are the registers to be set? Should we be looking at XMPAXH and XMPAXL registers?
    Please confirm if the above registers are the only way or if there are other mechanisms by which you can set the address extension registers.


    Query 2)
    Also, we are referring the slides available in the following link:
    training.ti.com/.../keystone-memory-slides.pdf

    In the above link : In slide 29, we understand that any access from CorePac to DDR3 uses 36 bit address. So, for that, do we
    have to do anything as application developers? What is your opinion?

    Query 3)
    Also, please throw some light on the bandwidth management feature in the above context. How is it inter-connected and what should we know about the same? In other words, in a multi-core setup can you confirm if bandwidth management feature could potentially help us avoid cache coherency issues. Also, is starvation bound registers the only way to enable the bandwidth management feature or are there other ways also?

    Thanks once again.

    Rgds,
    K J
  • 0 in reply to k j
    TI__Genius 12805 points

    K. J.

    I attach a presentation that I developed some time ago.  It describes the way the MPAX is working in addition to how the SES MPAX and the SMS MPAX

    Please read the presentation carefully.  If you still have issues,  please post them

    If it answers all your questions about this topic, please close the thread

    Regards

    Ran/cfs-file/__key/communityserver-discussions-components-files/791/0216.KeyStone-XMC-and-MPAX-Registers.pptx

  • 0 in reply to ran35366
    Prodigy 40 points

    Thanks Ran for sharing the PPT.

    We will go through the same and update you by EOD tomorrow. 

    Regards,

    KJ