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66AK2E05XABDA4 Keystone II NAND compatability

Alok Singh14
Intellectual 350 points
Other Parts Discussed in Thread: 66AK2E05

Can KeyStone II processor support MT29F512G08CKEABH7 NAND Flash? This flash 512 Gbit part. What is maximum density/size NAND Flash we can interface with KeyStone II?

Thanks,

Alok

  • 0
    TI__Guru** 114410 points
    Alok,

    Please check my response here. 66AK2E05 has the same EMIF IP for interfacing Async memory.
    e2e.ti.com/.../559765

    We couldn`t find the data sheet for this NAND device so if you have it on you, please check if it is ONFI 1.0 compatibility with ECC requirement and NAND geometry to determine if this NAND can be supported with K2E part.

    Regards,
    Rahul
  • 0 in reply to Rahul Prabhu
    Intellectual 350 points

    Rahul,

    Thanks for your prompt response.

    I checked the list of compatible NAND devices and could not find anything larger than 4 GB. We need minimum of 64 GB to meet our requirements. Can you suggest any compatible NAND devices or  even eMMC  that may meet our requirements. NAND device stated above is ONFI 3.0 compatible so it may not be compatible with KeyStone II.

    Thanks for your help.

    Alok

  • 0 in reply to Alok Singh14
    TI__Mastermind 46460 points

    Rahul,

    I understood that any limitations would be due to the hardware acceleration for ECC in the NAND block.  KeyStone-II devices support 1-bit and 4-bit for blocks up to 512 bytes in hardware.  However, if controlled solely through software, I was not aware of any limitations on block size or ECC implementation.  ONFI compatibility is required if the customer wants to boot from this NAND but if that is not the case, then it should be supported.

    Tom

  • 0 in reply to Tom Johnson 16214
    TI__Mastermind 46460 points

    Alok,

    I received additional confirmation.  The NAND support limitations in KeyStone-I and KeyStone-II devices only exist if this will be a primary boot device.  This is due to the requirement for ONFI 1.0 compliance and ECC support in hardware for 1 or 4 bit ECC on blocks up to 512 bytes.  However, if the block logic and the ECC logic are managed in software, there is no known limitation.  Also, if you desire to boot a large image from the NAND, you would need to boot into an intermediate boot loader that loads a NAND driver that can communicate with the large device.

    Tom

  • 0 in reply to Tom Johnson 16214
    Intellectual 350 points
    Thanks, Tom.
    Since KeyStone II only provides two R/B inputs (EMIF WAIT)- How can we interface NAND devices with more than 2 R/B signals? Can we use GPIO and manage in software? Some of the devices I am looking at has multiple R/B and CS signals.
  • 0 in reply to Alok Singh14
    TI__Mastermind 46460 points

    Alok,

    I believe that R/B can also be polled in some devices.  Is that an option for you?  I guess using a GPIO for R/B may also be possible.  If you run out of CS signals, then that could get really difficult.  Of course, you can implement a NAND solely on GPIO pins and control all of the pin transitions in software but that is extreme.

    Tom

  • 0 in reply to Tom Johnson 16214
    Intellectual 350 points
    Tom,
    I don't think R/B can be polled as this device has dedicated R/B and C/S signals per die ( total of 4 die). I will look around and see if I can find something that will work with KeyStone II and meet our requirement (higher density NAND).
    This was great help, a lot of good information.

    Thanks for all your help.
    Regards,
    Alok
  • 0 in reply to Alok Singh14
    TI__Mastermind 46460 points

    Alok,

    You should check with Micron.  The individual R/B status may still be able to be polled for each die.

    Tom