Cycle time of complex number multiplication/adding

Hi

There are many questions, I will start answering then one by one.

1  A pair of complex number (real 32bit + imaginary 32 bit) is multiplied by C66x core itself, how many cycles are needed in one complex multiplication?

>>>>  You did not mention if this is fixed point or floating point.  Assume it is floating point.   Look at www.ti.com/.../sprugh7.pdf  and do search for CMPYSP.

Next look in the compiler user guide http://www.ti.com/lit/ug/spru187u/spru187u.pdf 

    table 7-3 and see what is the intrinsic that calls CMPYSP (hint _cmpysp) and see how to use it and what other instructions are available. In general all assembly instructions take a single cycle or more cycles,  but they are all pipelined, that is, you can start instruction every cycle and get result every cycle (but with a delay). All use the M unit, so the core has two of them.     

2.    In same condition, if the complex multiplication (in case of #1 above) is done for 1024 times, how many cycles are needed?

>>>>  You can figure it out from the previous answer. The bottle neck is the memory access to L1 and L2. As you said correctly, complex number is 64 bits, so each multiplication requires reading two complex and writing back one complex, so at least one and half cycles (the bus to L1D is 2x64-bit)

If the data is in L2 reading it to the core takes more cycles.  Do search on the issue of L1 cache miss and see how many cycles it takes (I think that 5 but I may be wrong)

3.  If the data cannot be hit to the L2 Cache, how much penalty should we anticipate?

>>>> It depends on your architecture and your code.  The fastest way is to use double buffering and move data from DDR (say) to L2 using EDMA while the core is processing the previous buffer. In general any DDR values depends on the clock that you run the DDR and what other data movements are in the system.  I leave it to you to figure it out.

4. Complex ADD  -

>>>>  Do search in the two documents that I mentioned before for two floating point add operation (after all, complex add is like two real adds)

This is all for this posting

Ran

Hi Arai (44)

Here is what I would do in order to demonstrate the function from above:

1. I would find the DSPLIB function that does what the document says.  I assume, but you can verify it, that Complex block FIR - SP floating point is done by DSPF_sp_fir_cplx function.   Again, verify it.

Next I would run the unit test project.   it is part of the release - all unit test have an extension _d so for DSPF_sp_fir_cplx function the unit test is DSPF_sp_fir_cplx_d.c and verify that the linker command puts the data in L1D.

I think that all out benchmarks are done with data in L1D.  If the data is not in L1D many time the benchmark measure the data move and not the computation. Besides, if the data is not in L1D  other factors effect the result - like other data movements in the system.

(sometimes the data is in L2 and L1D cache is enable, this may work for long FIR where the cache miss is negligible compare to the computations)

Do what I suggest above and see if it works for you.   If not get back to me.

By the way,  my personal answer to TSIP  (and I do not have any knowledge about the specifics of TSIP) is that TSIP is a TDM bus.  You can move whatever you want in the bus as long as you obey the protocol (frame start, frame end, channels configured correctly) and the DSP can process the data anyway it is interleaved (because the DSP can have logic to do it). So the only question is if the source can generate the data in such a way that the TSIP can move it.    Just think about it

Regards

Ran

Hitoshi-san,

The C6000 architecture has 8 functional units that can execute an instruction each cycle.  There are two data units than are each capable of loading up to 64-bits of data from memory every cycle. These 64-bits can be 16-bit fixed point (so up to 4 16-bit values per side) or 32-bit fixed point (so up to 2 values per side) or 32-bit floating point (again up to two values per side).

The C66x has 2 multiply units and each multiply unit is capable of 16 16-bit multiplies or 4 32-bit multiplies.

Below is a table from the C66x instruction set guide SPRUGH7 that shows the load and multiply capability in terms of data size of the C66x.

As you noted the load limitation is 64-bits per side. So for 16-bit fixed point math, I can only bring in 4 new pieces of data per clock cycle per side. And for 32-bit single precision floating point or 32-bit fixed point I can only bring in 2 32-bit values per side. So for real multiplies where I need new data every cycle, I am limited to 2 multiplies and adds but for complex multiplies where the data can be reused, we can increase the number of multiplies done.

There also 4 other functional units that can be used for adds, logic expressions, compares or shifts. And these functional units can execute an instruction every cycle.

So with these 8 functional units you can load data, multiply and add data every cycle. Where the pipeline comes in is you are not multiplying and adding the data that was loaded from memory this clock cycle. When loading from memory there is a four cycle latency before the data is ready in the register. So you are actually multiplying the data that was read four cycles ago. Similarly when you are doing an add, you are not adding the value to the multiply you did this clock cycle you are actually adding the data from the multiply of the a previous cycle (different data types have different latencies for the multiply to complete; table 5-2 in SPRUGH7 is a good place to start).

Another question you had was on DSPF_sp_fir_cplx. That is a floating point function in DSPLIB. There are fixed point and floating point implementations of most common DSP functions (FIR, FFT, IIR, etc). When you see sp it means single precision floating point.

I hope this answers your question on how it is possible to load data, do a multiply and add all in one cycle.

If something is not clear, please let me know and I will try to clarify further.

Jackie B.