Other Parts Discussed in Thread: SYSBIOS
Tool/software: TI-RTOS
Hi,
In my project, which should receive data from FPGA via RIO and send some intermediate results via TCP, I suffer from random exceptions in different places and under random conditions.
Spending several hours, investigating the situation, I found that most likely the reason was L1/L2 cache non-coherence. This issue discussed many times here in various circumstances.
Original TCP client application, which I took as a reference, mix BIOS and CSL Cache functions.
It seems that CSL Cache functions are not multitask environment safe.
Working on this issue I walked through the BIOS code (ti/sysbios/family/c66/Cache.c file) and found that some peaces of code may also cause problem.
1. BIOS Cache_xxx() c66x family specific implementation totally ignore cache type parameter (third argument of BIOS Cache_xxx() call), but operate with L2 cache control registers instead.
This shouldn’t cause any troubles when block cached in L1/L2, as L2 cache operations should make appropriate updates in L1 also, but this may not work when L2 cache is not used for the block or disabled.
2. Address alignment in function Cache_block() is not correct, as it is aligned on double word boundary, instead of cache line size. This cause incorrect byte aligned value calculation.
3. Function Cache_block() check cache module ready state, reading L2 Write Word Count control register, which is the mirror of 2 other L2 Word Count control registers, but this is not a case for checking L1 cache ready, I guess.
4. Wait parameter of Cache_xxx() (fourth argument of BIOS Cache_xxx() call) ignored except last cache block operation when xdc Cache_atomicBlockSize parameter has default non-zero value. It should be better if function only wait for cache module ready condition then program cache control registers and return without waiting, when wait parameter is not set.
Some extra. DSP silicon designer should implement shadow control registers mechanism in the cache module, similar to what was introduced in the other processor subsystems, like RIO. It would avoid loosing DSP performance, while check and waiting cache module ready in multi-task environment.