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66AK2G02: Selecting converters for power rails

Part Number: 66AK2G02

Hi team,

I noticed on the ICE board that discrete converters are used instead of a PMIC to power the K2G. I have a customer wanting to take the same approach.

I am in the process of making part recommendations for these converters, and I noticed on the ICE board most of the core rails are just powered by switchers and not any low noise LDOs. Is there not any low noise requirements/recommendations for these rails? Switching noise on all the CVDD/AVDD/DVDD rails is ok?

The ICE board has extra stuff being powered from these rails that my customer wont be using, so I am not going to copy that boards power tree. As I start my search I wanted to make sure that I wasn't going to pick some converter that would upset the processor with switching noise. 

Thanks,

Brian

  • Hi Brian,

    I've forwarded this to the design experts. Their feedback should be posted here.

    BR
    Tsvetolin Shulev
  • Hi Brian,

    For keystone devices in terms of power management, you should follow the recommendations given in datasheet & the bellow wiki:
    processors.wiki.ti.com/.../Keystone_Multicore_Device_Family_Schematic_Checklist

    In case of any discrepancy between EVM & datasheet, you must follow the datasheet recommendations.

    Is there not any low noise requirements/recommendations for these rails? Switching noise on all the CVDD/AVDD/DVDD rails is ok?


    The noise requirements are described in the Hardware Design Guide for Keystone II devices (www.ti.com/.../sprabv0.pdf). Refer to Chapter 2 Power Supplies.

    Best Regards,
    Yordan
  • I have a couple of follow up questions:

    • As a quick first question, does this design guide also apply to the K2G? Some of the guide seems to give conflicting answers to questions I have asked the K2G internal teams already (for instance, using the power estimator tool to calculate the max power your supplies need. I was told by teams to strictly follow a chart that they gave me offline, regardless of customer application, and not use the power supply estimator to calculate your max current.)

    • Next, in the design guide, the power supply section basically just lists some ferrites to be used instead of filters, and LDOs are not mentioned. There doesn’t seem to be an actual noise spec for me to follow when choosing LDOs.

    • Also, the rails it calls out for “Keystone II” devices are close but not actually the same as the rails that exist on the K2G02 device. See how the rails in the two charts are a bit different, like CVDD/CVDD1, a lack of VP/VPTX, and a 1.35V supply for VDD_DDR:

  • Hi,

    I've asked the design team for help. Their feedback should be posted here.

    Best Regards,
    Yordan
  • Hi Brian,

    While waiting for a reply from the design team.
    Here is what I can answer:
    As a quick first question, does this design guide also apply to the K2G?

    Yes, currently this is the only available hardware design guide for Kyestone II devices, that we have.

    There doesn’t seem to be an actual noise spec for me to follow when choosing LDOs

    This information should be available in section 5.4 of K2G data manual. For each analog power rail there should be a given "Maximum noise (peak-peak)" parameter, BUT because K2G is fairly new design this is obviously not available yet. Should be added in future DM releases.

    Also, the rails it calls out for “Keystone II” devices are close but not actually the same as the rails that exist on the K2G02 device. See how the rails in the two charts are a bit different, like CVDD/CVDD1, a lack of VP/VPTX, and a 1.35V supply for VDD_DDR


    The Keystone II HW design guide is a general document that aims to summarize the design guide for ALL KS2 SoCs (K2L, K2E, K2G, K2H etc..). This is why there are some differences between sprabv0 & K2G Data Manual.

    Hope this helps.

    Best Regards,
    Yordan