TMS320C6678: C6678LE EVM DDR3 is not stable

Naoki Kawada

Guru 19890 points

Part Number: TMS320C6678

Hello,

My customer has some C6678LE EVMs and they found DDR3 write/read was not stable on one of them. It sometimes works, but does not work. Other EVMs work perfectly. They are using CCSv6.1.3 with integrated gel file (C:\ti\ccsv6\ccs_base\emulation\boards\evmc6678l\gel\evmc6678l.gel). According to logs on CCS console window, DDR3 initialization in gel file seems to be done correctly. But for example, if they dump data from memory window view, CCS shows an error of data verification.

I know the gel file has a problem with DATA_REG_PHY_DQ_OFFSET Programming. Please see the following post:

Even if we do the same thing here, the problem is still existing. Do you have any experience about this issue ? If so please share your workaround for this issue.
Or, should we initiate the replacement process to your local sales team ? Please suggest.

Lastly, the above fix is not present in the later version of CCS. For example, I don`t see any fix in gel file bundled in CCSv7. Is this minor problem ? For me, I feel the fix should be merged to your master gel file.

Best Regards,
Naoki

over 7 years ago

0 Yordan Kovachev over 7 years ago

TI__Guru**** 161600 points

Hi Naoki,

I've notified the design team. Their feedback will be posted here.

Best Regards,
Yordan

0 Tom Johnson 16214 over 7 years ago in reply to Yordan Kovachev

TI__Mastermind 46460 points

Naoki-san,

Is this a new C6678 EVM with this problem or one that you have had in service for some time? When was it purchased? Did it work successfully for a time?

Tom

0 Tom Johnson 16214 over 7 years ago in reply to Tom Johnson 16214

TI__Mastermind 46460 points

Naoki-san,

The DQS offset timing erratum that requires the extra write for C665x devices does not exist in C667x devices. Therefore, it is not needed in the GEL.

Tom

0 Naoki Kawada over 7 years ago in reply to Tom Johnson 16214

Guru 19890 points

Hello, Tom

I`m asking the customer about the purchase date.
As for DQS offset timing erratum, the following manual does not state that fact. This manual should be commonly referred for DDR3 initialization on KeyStoneI devices. Is this eratta really applied only for C665x ? Let me clarify again.

www.tij.co.jp/.../sprabl2e.pdf

Best Regards,
Naoki

0 Tom Johnson 16214 over 7 years ago in reply to Naoki Kawada

TI__Mastermind 46460 points

Naoki-san,

Please refer to the text more closely:

The category names are confusing. However, these are defined back in Table 1. The C667x DSPs are in the "Combined Fixed Ratio Register DSPs" group and the C665x DSPs are in the "Expanded Fixed Ratio Register DSPs" group.

Tom

0 Tom Johnson 16214 over 7 years ago in reply to Tom Johnson 16214

TI__Mastermind 46460 points

Previous post edited to add image a second time.

0 Naoki Kawada over 7 years ago in reply to Tom Johnson 16214

Guru 19890 points

Hello, Tom

Thanks for your clarification, I understood. Anyway, I`ll update you later about purchase date.

Thanks,
Naoki

0 Naoki Kawada over 7 years ago in reply to Naoki Kawada

Guru 19890 points

Tom,
Sorry to ask you so many things, but what could happen when DQS offset timing erratum was applied to C667x ? If a write operation was actually done on C667x, is the behavior of DDR3 initialization changed ? Or, no effect ?
Best Regards,
Naoki

0 Tom Johnson 16214 over 7 years ago in reply to Naoki Kawada

TI__Mastermind 46460 points

Naoki-san,

There should be no effect. The register should already contain that value from reset release.

Tom

0 Naoki Kawada over 7 years ago in reply to Tom Johnson 16214

Guru 19890 points

Hello, Tom

It is good to know that. Thank you for your information.
As an aside, I run my eyes through the source code of Board library and Platform library bundled in C665x PDK. I seem the workaround for the errata is not existing in DDR3 initialization code. I think it is better for your software team to review the code:

C:\ti\pdk_c665x_2_0_5\packages\ti\platform\evmc6657l\platform_lib\src\evmc6657.c
C:\ti\pdk_c665x_2_0_5\packages\ti\board\src\evmC6657\evmC6657_ddr.c

So, about purchase date. They got the EVM in 02 Oct 2016. But unfortunately, they could not state the problem is seen in early phase.

Best Regards,
Naoki

0 Tom Johnson 16214 over 7 years ago in reply to Naoki Kawada

TI__Mastermind 46460 points

Naoki-san,

The C6678 EVM ships with an Out of Box Demo and a Power on Self Test. Please provide the results when running the POST software. You may need to make sure it completes successfully on a passing board before as a comparison to the failing board.

Tom

0 Tom Johnson 16214 over 7 years ago in reply to Tom Johnson 16214

TI__Mastermind 46460 points

Naoki-san,

You reported a deficiency in the C665x PDK software. Please provide the version of Processors SDK that you are using.

Tom

0 Naoki Kawada over 7 years ago in reply to Tom Johnson 16214

Guru 19890 points

Tom,

It is the latest ProcSDK (Release 03.03.00). As for POST, I'll check it later and update you once I get the result.

Thank you.
Naoki

0 Naoki Kawada over 7 years ago in reply to Naoki Kawada

Guru 19890 points

Hello, Tom

They tried POST, but they could not see any error with POST. What can we do for this issue ? I have no idea about this.

Best Regards,
Naoki

0 Tom Johnson 16214 over 7 years ago in reply to Naoki Kawada

TI__Mastermind 46460 points

Naoki-san,

The POST contains a DDR configuration. Can they connect CCS and run a SDRAM test after POST completes?

If it still fails, please provide a log of the failures showing data written and erroneous data read. Also, provide a description of the DDR test program.

Tom

0 Naoki Kawada over 7 years ago in reply to Tom Johnson 16214

Guru 19890 points

Tom,

I decided to get their EVM and will try to look into this here here. I`ll update you later.

Best Regards,
Naoki

0 Naoki Kawada over 6 years ago in reply to Naoki Kawada

Guru 19890 points

Hello, Tom

I got their EVM and did some tests at my side, but I could not see any error with it :-( I returned it to them.

BTW, did you get any feedback from your software team about C665x DDR3 initialization in PDK ?

Best Regards,
Naoki

0 Tom Johnson 16214 over 6 years ago in reply to Naoki Kawada

TI__Mastermind 46460 points

Naoki-san,

I have filed a Jira ticket to get the C665x DDR3 initialization updated in the ProcSDK. It should be integrated into the next regularly scheduled release which should be available in about 3 months.

Tom

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TMS320C6678: C6678LE EVM DDR3 is not stable