Hello,
There is a booting fail issue on my custome board.
I opened a thread before but am createing new one because I did not get any idea.
Boot mode is emif16 - NOR flash.
After power on, DSP is initialized by NOR flash data then app sw is copied from NOR to DDR3.
When boot failed, the DDR3 clock is same frequency to reference clock. When I checked DDR3PLLCTL register, BYPASS mode was enabled.
Initialization function is almost same to evmc6678.gel which is GEL file for c6678 eva board.
Anyhow I have some questions about PLL and DDR init.
1> DDR3 leveling
Currently ddr3 clock is set to 666.7MHz. I want to reduce it to 400MHz. Should I change 'ddr3_setup_auto_lvl_1333()' function?
Max clock DDR3 memory supports is 666.7MHz. I will just reduce clock speed by changing PLL value, but I am not sure if leveling function should be changed or not.
I cannot find out spreadsheet mentioned in 'KeyStone I DDR3 Initialization' pdf file. Where can I download it?
2> How to check PLL lock state
In PLL initialization sequence, there is only minimum time to wait for PLL lock.
Is there no way to check PLL lock status?
If PLL is still unlock state after minimum waiting time, should I increase waiting time and try test again?
3> GOSTAT bit
Init_PLL() in GEL file put error text out and do nothing when GOSTAT is not changed to 0.
In application, can I reset DSP by clear RSTCTRL register?