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TMS320C6678: some questions about c6678 init - checking pll lock, ddr3 leveling

Part Number: TMS320C6678

Hello,

There is a booting fail issue on my custome board.

I opened a thread before but am createing new one because I did not get any idea.

Boot mode is emif16 - NOR flash.

After power on, DSP is initialized by NOR flash data then app sw is copied from NOR to DDR3.

When boot failed, the DDR3 clock is same frequency to reference clock. When I checked DDR3PLLCTL register, BYPASS mode was enabled.

Initialization function is almost same to evmc6678.gel which is GEL file for c6678 eva board.

Anyhow I have some questions about PLL and DDR init.

1> DDR3 leveling

Currently ddr3 clock is set to 666.7MHz. I want to reduce it to 400MHz. Should I change 'ddr3_setup_auto_lvl_1333()' function?

Max clock DDR3 memory supports is 666.7MHz. I will just reduce clock speed by changing PLL value, but I am not sure if leveling function should be changed or not.

I cannot find out spreadsheet mentioned in 'KeyStone I DDR3 Initialization' pdf file. Where can I download it?

2> How to check PLL lock state

In PLL initialization sequence, there is only minimum time to wait for PLL lock.

Is there no way to check PLL lock status?

If PLL is still unlock state after minimum waiting time, should I increase waiting time and try test again? 

3> GOSTAT bit

Init_PLL() in GEL file put error text out and do nothing when GOSTAT is not changed to 0.

In application, can I reset DSP by clear RSTCTRL register?

  • Hi,

    I've notified the design team. Their feedback will be posted here.

    Best Regards,
    Yordan
  • Yoonsun,

    I can answer the DDR3 questions:

    After power on, DSP is initialized by NOR flash data then app sw is copied from NOR to DDR3.  When boot failed, the DDR3 clock is same frequency to reference clock. When I checked DDR3PLLCTL register, BYPASS mode was enabled.

    TI: Have you loaded a program into internal memory through NOR that validates PLL configuration and DDR3 robustness?  This needs to be validated before loading a program into DDR3.

    Currently ddr3 clock is set to 666.7MHz. I want to reduce it to 400MHz. Should I change 'ddr3_setup_auto_lvl_1333()' function?

    TI:  Absolutely!  All SDRAM timing values and leveling configuration values are related to the clock rate.  These need to be updated for 400MHz (800MT/s) operation.

    Max clock DDR3 memory supports is 666.7MHz. I will just reduce clock speed by changing PLL value, but I am not sure if leveling function should be changed or not.

    TI:  No, as stated above, this is not valid for leveling or for the SDRAM configuration.

    I cannot find the spreadsheet mentioned in 'KeyStone I DDR3 Initialization' pdf file. Where can I download it?

    TI.  The link on TI.COM appears to be broken.  I will ask for this to be fixed.  I have attached the ZIP file to this post.

    After power on, DSP is initialized by NOR flash data then app sw is copied from NOR to DDR3.  When boot failed, the DDR3 clock is same frequency to reference clock. When I checked DDR3PLLCTL register, BYPASS mode was enabled.

    TI:  This indicates that the boot code is not proper.  Please follow the steps in the PLL UG and the DDR3 Initialization Guide.

    Tom

    2630.DDR3 Initialization sprabl2.zip

  • Yoonsun,

    Regarding the PLL configuration, be sure to follow the sequence shown in the PLL UG that is also implemented in the GEL file.  This is known to be robust.  It is also implemented in the PDK code properly.  Make special note of the stall/delay steps in the sequence.  These must be properly implemented in your compiled code such that the optimizing compiler does not strip them out.  This is also true od the stall/delay steps in the DDR3 initialization.

    Tom

  • Yoonsun,

    The link to the spreadsheets in SPRABL2E has been fixed.

    Tom

  • Tom,

    Can you let me know which folder PDK code source is in?

  • Hi,

    You can download the Processor SDK RTOS from here:
    www.ti.com/.../processor-sdk-c667x

    Best Regards,
    Yordan
  • The DDR and PLL initilaization files are provided as part of the evmC6678 board library inside PDK.

    Please locate the sequence and the initialization in the following files in Processor SDK RTOS 3.x
    * pdk_c667x_x_x_x\packages\ti\board\src\evmKeystone board_pll.c
    * pdk_c667x_x_x_x\packages\ti\board\src\evmC6678\evmC6678_pll.c
    * pdk_c667x_x_x_x\packages\ti\board\src\evmC6678evmC6678_ddr.c

    Regards,
    Rahul