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RTOS/TMS320C6678: Running VLFFT application using CCS on custom board

S Siddiqui
Intellectual 385 points
Part Number: TMS320C6678
Other Parts Discussed in Thread: FFTLIB

Tool/software: TI-RTOS

We are trying to run the VLFFT example on Ti C6678 DSP on custom board using XDS100v1 emulator. The program loads successfully on all cores. When the the program steps over IPC_Start., the console shows the output similar to that as shown below.


[C66xx_0] A0=0x840012f0 A1=0x2c
A2=0x0 A3=0xfffffffa
A4=0x84000008 A5=0x0
A6=0x835d14 A7=0x0
A8=0xa0000 A9=0x2
A10=0x840012f0 A11=0x835d14
A12=0x8346e8 A13=0x82f93c
A14=0x840012f0 A15=0x0
A16=0x84001314 A17=0x0
A18=0x840012e8 A19=0x20
A20=0x0 A21=0x0
A22=0xad94eff6 A23=0x41108910
A24=0xc328832a A25=0x5c880800
A26=0xdda8acf7 A27=0x80960620
A28=0x94000e02 A29=0x831b0c
A30=0x20 A31=0x0
B0=0x0 B1=0x0
B2=0x0 B3=0x811c00
B4=0x82f93c B5=0x0
B6=0x835d78 B7=0xc
B8=0x1c B9=0x0
B10=0x8313d0 B11=0x835d78
B12=0x0 B13=0x0
B14=0x836f20 B15=0x835cc8
B16=0x831744 B17=0x0
B18=0xa B19=0x78
B20=0x8 B21=0x69
B22=0xf B23=0x0
B24=0x2120104 B25=0xb4008005
B26=0xd8802002 B27=0x7afb2b33
B28=0x44958234 B29=0xce11dc70
B30=0xc10c680 B31=0x0
NTSR=0x1020f
ITSR=0xf
IRP=0x828420
SSR=0x0
AMR=0x0
RILC=0x0
ILC=0x0
Exception at 0x84000300
EFR=0x2 NRP=0x84000300
Internal exception: IERR=0x18
Opcode exception

ti.sysbios.family.c64p.Exception: line 255: E_exceptionMin: pc = 0x84000300, sp = 0x00835cc8.
To see more exception detail, use ROV or set 'ti.sysbios.family.c64p.Exception.enablePrint = true;'

1) We would appreciate any help in running the VLFFT application in debug mode using CCS.

2) Does the GEL file needs to be loaded on core 0 only or all cores.

  • 0
    TI__Guru**** 161600 points
    Hi,

    Which SDK version is this?

    Best Regards,
    Yordan
  • 0 in reply to Yordan Kovachev
    Intellectual 385 points
    Hi,

    Thanks for the reply.

    The products we are using to compile the VLFFT project are listed below along with versions.

    XDCTools 3.23.4.60
    EDMA3 LLD 2.11.5
    CtoolsLib 2.2.0.00
    IPC 1.24.3.32
    MCSDK 2.1.2.6
    SYS/BIOS 6.33.6.50


    CCS 5.3


    Best Regards
  • 0 in reply to S Siddiqui
    TI__Genius 9065 points
    Siddiqui,

    Where did you download the VLFFT sw?

    GEL files is only needed for one of the cores assuming you connect that core first. By default people use core 0.

    regards,
    David
  • 0 in reply to dzhou
    Intellectual 385 points
    David,

    The software I downloaded was the one from e2e.ti.com/.../303599

    But when I built the program (as it was provided) it gave linker error #10099-D placement with alignment failed for following regions
    .fardata
    .const
    .stack
    .cio
    .cinit
    .switch

    The linker tries to put all the above sections in L2SRAM.
    I moved the above sections to DDR3 on my custom board. The program build was successful but it hanged at IPC_start with above mentioned errors.

    Best Regards
    Siddiqui
  • 0 in reply to S Siddiqui
    TI__Genius 9065 points
    Siddiqui,

    The code you downloaded is not part of standard release so not being properly maintained. We can take a look at it but please expect some delays.

    Meanwhile, you can use the latest DSP libraries within the Processor SDK RTOS package. This is actively supported.
    software-dl.ti.com/.../index_FDS.html

    best regards,
    David Zhou
  • 0
    Intellectual 385 points

    Part Number: TMS320C6678

    I would like to know how Xiaohui measured FFT performance in terms of cycle count for his paper , "Very large FFT for TMS320C6678 processors".

    Regards

     

  • 0
    TI__Guru 65405 points
    Hi Siddiqui,

    I've forwarded this to the software experts. Their feedback should be posted here.

    BR
    Tsvetolin Shulev
  • 0 in reply to Cvetolin Shulev-XID
    TI__Guru** 114410 points
    I am not the subject matter expert as in case of Xiaohui...but I checked internally and here is the response from the development team:

    "The very large FFT project (vlfft) was built as an example how to use 8 cores for large FFT. One of the main ideas in the code was the usage of EDMA to move data from DDR (the example was for 1M complex floating point FFT that is 8M bytes of data) to L2 concurrently with the DSP processing. The memory management was very important to the project to get best performances by using double buffers (ping pong buffers).
    The code used an older version of the EDMA drivers. A few years ago a new version of EDMA drivers were released that needs more memory for control structures, and while the difference is very small, the new drivers cannot fit into the L2 memory. Thus you cannot build the old source unless you make some changes.

    The good news is that the fftlib library has a support for large FFT - look at the way 2D FFT is implemented and read documents how the large FFT algorithm is working. Look for example at www.ti.com/.../spry277.pdf "

    Regards,
    Rahul