# TMS320C6657: C6657 Power-down sequence

Hello,

I'm sorry but, I rewrote the whole sentence as below because my explanation was not appropriate.

I'll use LM3881 to control the power-on and power-off sequence of C6657. During the power-off sequence, the source power supply of LM3881 will power down first and the correct power-off sequence to C6657 may not be performed. In the worst case, an inappropriate voltage difference of 1.8 V (or more) may occur between each power supply rail. Therefore, I'm thinking about inserting a diode between the input and output of each power supply IC. And at least, the voltage difference can be reduced to the VF level (about 0.4 V) of the diode. Also in this case, for example, 0.4 V may be applied to CVDD1 (1.0 V) in spite of CVDD (SmartReflex) being 0 V. (CVDD1 should be 0 V first.) Is there a possibility that this inappropriate voltage difference of 0.4 V may damage C6657?

Regards,
Kazu

• Hi Kazu,

I've forwarded this to the design experts. Their feedback should be posted here.

BR
Tsvetolin Shulev

• Additional details from field team

Customer can start to power down each power rail in order of the specification by using the sequence IC such like LM10011, etc. with main power source (5V/3.3V), but a little charge may remain during the sequence IC can’t work, because the falling timing of main power source is very close to that of each power rail (CVDD, CVDD1, DVDD15 and DVDD18).

Therefore, they’re considering to insert a diode between each power rail. By this method the power down sequence can be kept until diode’s VF level (approx. 0.4V), but it may not be able to be kept at the quite low voltage level (0.4V to 0V).
For example, (case of CVDD1 and CVDD)
- CVDD1 can be powered down earlier than CVDD according to the specification.
- CVDD1 can reach around 0.4V earlier than CVDD.
- However, CVDD may reach 0V earlier than CVDD1 at the quite lower voltage levwl (0.4V --> 0.0V) .
This is opposite order of the specification.

In the same manner, the violation of the power down sequence may occur during 0.4V to 0.0V in the following cases also.
CVDD <--> CVDD1
CVDD <--> DVDD18
CVDD <--> DVDD15
CVDD1 <--> DVDD18
CVDD1 <--> DVDD15
DVDD18 <--> DVDD15

Can these possibilities be permitted at the quite low voltage ?
Does this violation impact a device any damage ?
Or could you tell them a recommended circuit to solve this problem if you have any idea ?

• In reply to Mukul Bhatnagar:

Hello Experts,

http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/140558

The first is a controlled power down of the DSPs while the rest of the system remains active.

I can control it with the LM3881.

We recognize that a in a total power down of the system it's difficult to provide any sequencing but in that case none of the power rails will be present for a changed longer time.

In this case, I'm considering to insert a diode to reduce damage to device. But according to the above, it seems unnecessary to do that. Is my understanding correct?

Regards,
Kazu

• In reply to Kazu Kon:

Kazu,

The information provided is too vague.  Please provide scope captures showing both the power up and power down sequences.  Preferably, a single capture showing all 4 supply rails simultaneously will be most useful.  Also, please explain how the power down event is initiated?

Tom

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• In reply to Tom Johnson 16214:

Hello Tom,

I'm sorry for confusing you. Also I don't have any oscilloscope captures because of the design stage now. The power down for our system is total power down. It's difficult to provide a power down sequence to the C6657 because a source power supply IC of each power rail IC is turned off quickly during the time. Could I ask you just two questions?

1. According to the following thread, it seems to be unnecessary to care the power down sequence in C6670 when total power down of the system. I believe that this also applies to C6657. Is it correct?

http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/140558

2. If I insert a diode between each power rail, at the end of the power down of C6657, 0.4 V opposite voltage may be applied to each supply rail. For example, 0.4 V is applied to CVDD1 (1.0 V) in spite of CVDD (Smart Reflex) being 0 V. Then this state may continue several milliseconds seconds until CVDD1 drops to 0V. Does this violation impact a device any damage?

Regards,
Kazu

• In reply to Kazu Kon:

Kazu,

I'm sorry for confusing you.

TJ: It is not that you are confusing me.  When I say the information is vague, I am indicating that the provided information is not precise and does not have enough detail.

Also I don't have any oscilloscope captures because of the design stage now. The power down for our system is total power down.  It's difficult to provide a power down sequence to the C6657 because a source power supply IC of each power rail IC is turned off quickly during the time.

TJ: What does this mean?  Are you saying that a single supply voltage (such as 5V) is feeding all 4 DSP power supplies and that when it is turned off, all 4 of the DSP supplies than collapse simultaneously?  The details are important.

Could I ask you just two questions?

1. According to the following thread, it seems to be unnecessary to care the power down sequence in C6670 when total power down of the system. I believe that this also applies to C6657. Is it correct?

TJ: The post still says that the proper method to power off the DSP is to bring down the supplies in the reverse of a valid power-up sequence.  There is allowance for all to come down simultaneously.  However, bulk capacitance and load variations may affect the discharge rate of each DSP supply.  This needs to be analyzed.

2. If I insert a diode between each power rail, at the end of the power down of C6657, 0.4 V opposite voltage may be applied to each supply rail. For example, 0.4 V is applied to CVDD1 (1.0 V) in spite of CVDD (Smart Reflex) being 0 V.  Then this state may continue several milliseconds seconds until CVDD1 drops to 0V.  Does this violation impact a device any damage?

TJ: Reversing the levels between CVDD and CVDD1 can potentially result in significant current in the memory arrays.  This must be prevented.  Adjustments to the bulk capacitance may be sufficient in a simultaneous shutdown to avoid this voltage reversal.  Adding a voltage monitoring device such a TPS3808 to the main supply voltage can also be a solution to start shutting down the DSP supplies in the proper order before the shut-down becomes uncontrolled.  The diode solution might not be sufficient.  This is why scope captures need to be reviewed for final design approval.

Tom

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• In reply to Tom Johnson 16214:

Hello Tom,

I appreciate your kind support. We're considering the attached power block. I'll review the circuit to avoid voltage reversal between each power supply. Please let me know if you have any idea.

Regards,
Kazu

c6657_power.pptx

• In reply to Kazu Kon:

Kazu,

The diagram provided matches my expectations.  I have a few questions:

1. What is the voltage between the primary DC/DC and the 4 supplies the create the DSP supply voltages?
2. What is the input voltage to the primary DC/DC?
3. You mention that the LM3881 starts the shut-down sequence but the output from DC/DC collapses before the sequence completes.  What event triggers the shut-down start (i.e. drives the EN low on LM3881)?
4. What is the delay time between LM3881 outputs (or what is the Tadj cap value)?

Please see the attached diagram.  It shows an implementation where the TPS3808 detects the collapse of the main DC input voltage.  The diode and bulk capacitance keep the DC/DC in regulation longer.  The Tadj can be adjusted so that all supplies are shut down in a controlled manner.

Additionally, the output from the TPS3808 can be connected to logic controlling the PORz into the C6657 DSP.  By driving PORz low during the shut-down sequence, current draw is reduced.  Also, this prevents output contention with other connected devices during the shut-down event.

Tom

2664.c6657_power.pptx

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• In reply to Tom Johnson 16214:

Hello Tom,

Tom Johnson 16214

1. What is the voltage between the primary DC/DC and the 4 supplies the create the DSP supply voltages?

We are considering 5V or 3.3V but haven't decided yet.

Tom Johnson 16214

2. What is the input voltage to the primary DC/DC?

It's 24V supplied from the external board.

Tom Johnson 16214

3. You mention that the LM3881 starts the shut-down sequence but the output from DC/DC collapses before the sequence completes.  What event triggers the shut-down start (i.e. drives the EN low on LM3881)?

When the normal shutdown, the power-off sequence can be performed normally. But if the external power source turns off suddenly, the source power supply will be dropped before the shutdown sequence is completed. I wonder if how far we need to take a measures...

Tom Johnson 16214

4. What is the delay time between LM3881 outputs (or what is the Tadj cap value)?

It's still under consideration. It may be in time for the completion of the sequence by shortening the power-off sequence time. As a precaution, we're considering other measures which are independent of the time.

Regards,

Kazu

• In reply to Kazu Kon:

Kazu,

It is fortunate that you have an upstream DC voltage of 24 volts.  This is the supply rail that should be monitored by the TPS3808 through a voltage divider.  The capacitors on the 24V rail will contain a large amount of energy.  If you implement the diode, caps and TPS3808 as I suggested, you will have time to shut down the DSP supplies in the proper sequence; even when the main power is cut.  You will be able to tune the LM3881 delays to sequence the supplies off with plenty of time margin.

Tom

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