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TMS320C6678: PCIe Data Space Limitation

Part Number: TMS320C6678

Hi,

     Our C6678 is configured as EP and we would like to access more than 256MB on the RC side. Is there a way to do so without changing the OB_OFFSET_INDEX register values? If I would like to send MSI interrupts, am I forced to use an outbound translation window (i.e. within address range 0x60000000 - 0x6FFFFFFF) to write MSI_DATA to the RC's IRQ register?

Best Regards,

Johnny

  • Hi Johnny,

    I've forwarded this to the PCIe experts. Their feedback should be posted here.

    BR
    Tsvetolin Shulev
  • Hi,

    What is the RC side, does it support IB translation? For example, suppose RC side is also a TI 6678. The OB window is limited to 256MB (0x6000_0000 to 0x6fff_ffff) on EP side, and you want to use EP to generate OB R/W for more than 256MB, then you can change RC side IB translation to map into different memory segment. Like at time 1, accessing EP side 0x6000_0000 translate into RC side DDR region 0x8000_0000. Then at time 2, you can change RC side inbound to 0x9000_0000. At time 3, EP 0x6000_0000 is linked RC's 0x9000_0000 (an different DDR region).

    Regards, Eric
  • RC side is an Intel chip running Windows 10. Is changing the IB translation window the only solution to this problem?

  • Hi,

    So RC side is just a Windows host. In normal case, Windows PC has the PCIE driver. The RC intiaiates the PCIE R/W transaction, you can change the IB of C6678 to let it landed at different memory locations (DDR, MSMC, L2 ...).

    If you use EP (C6678) to intiaiates the PCIE R/W, then it goes through the OB translation limited by 256MB window. And you don't want to change OB, and you can't change the IB of Windows. Then, there is no way to overcome it.

    Regards, Eric