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Is sprugs6d.pdf the serdes pcie's specifaction document?

Hi

Is sprugs6d.pdf the serdes pcie's specifaction document?

When I try to check the init code in csl_wiz8_sb_refclk100MHz_pci_5Gbps function.

I find the meaning of registers are not match.

for example

 CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0000),15, 8, (uint32_t)0x08);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0060), 7, 0, (uint32_t)0x5c);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0060),15, 8, (uint32_t)0x1c);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0060),23,16, (uint32_t)0x04);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0064),15, 8, (uint32_t)0xc7);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0064),23,16, (uint32_t)0x43);
  CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0064),31,24, (uint32_t)0x03);

base_addr is 0x2320000

I can't find register "base_addr + 0x0060". And "base_addr + 0x0064" 's reigster , from bit 2~31 are reserved according to sprugs6d.pdf.

could you tell me why? or i'm checking the wrong specifiction ?

Thanks

  • I've forwarded this to the PCIe experts. Their feedback should be posted here.

    BR
    Tsvetolin Shulev
  • Hi,

    It looks that you are using Keystone II device. The Serdes document is: www.ti.com/.../spruho3a.pdf

    The www.ti.com/.../sprugs6d.pdf is the PCIE user guide.

    I don't know the exact SOC you are using. If it is Keystone I, the Serdes register is 0x262_0390 and 0x262_0394.

    If it is Keystone II, as you mentioned csl_wiz8_sb_refclk100MHz_pci_5Gbps, then please look at the SOC datasheet for Serdes base address, some device can have two PCIE interfaces. If you are only taking about PCIE 0, yes, its Serdes dase address is 0x232_0000.

    Regards, Eric
  • Hi

        yes I 'm using keystone II and PCIE 0.

        My purpose is to generate PRBS-31 and set SERDES PCIE to be loopback. And test the signal.

        My status now :

        I already use csl_wiz8_sb_refclk100MHz_pci_5Gbps to init the serdes pcie port.

        also I enabled the lanes by using CSL_SerdesLaneEnable function.

        Then I try to use  "devmem 0x2180223c 32 0x00249c80"  to set serdes pcie to be loopback mode, 

        This action cause system crash.

        This situation looks like after initialization, the SERDES PCIE port is dead.

         So I try to check the register setting in  csl_wiz8_sb_refclk100MHz_pci_5Gbps function.

        I compare the reigster setting with the value in  www.ti.com/.../sprugs6d.pdf document.  I find the meaning of registers are not match

        For example:

        base_addr is  0x2320000

       (1)

      CSL_FINSR((base_addr + 0x0060), 7, 0, (uint32_t)0x5c);
      CSL_FINSR((base_addr + 0x0060),15, 8, (uint32_t)0x1c);
      CSL_FINSR((base_addr + 0x0060),23,16, (uint32_t)0x04);

      I can't find "base_addr + 0x0060" in specifaction.

       (2)  

      CSL_FINSR((base_addr + 0x0064),15, 8, (uint32_t)0xc7);
      CSL_FINSR((base_addr + 0x0064),23,16, (uint32_t)0x43);
      CSL_FINSR((base_addr + 0x0064),31,24, (uint32_t)0x03);

       in specifaction. 64h is  EP_IRQ_SET , bit from 2-31 are Reserved

    So could you give me some advice to solve PCIE dead problem?

    Thank you in advance

  • Hello
    Thank you for your information.
    I find that we have a blackhawk. So I tried the CCS.
    I installed CCS6.1.2.00015_win32 and ti-processor-sdk-rtos-k2hk-evm-02.00.01.07-Windows-x86-Install.exe.
    Then I loaded the serdes_diag_prbs_K2KC66ExampleProject.
    Enabled the #define serdes_diag_test_phy_type TEST_SERDES_PCIe in serdes_diag_platform.h, and
    try to do the Serdes_Example_PRBSTest.
    When I run the test in k2k board. there is no PRBS signal come out. I test the clock, clock is
    working in 100MB
    So could you check the serdes_diag_prbs_K2KC66ExampleProject code if the serdes PCIE prbs test
    code is right or not.
    Thanks
    BRs
    Wei Wang
  • Hello

    I find that we have a blackhawk. So I tried the CCS. I installed CCS6.1.2.00015_win32 and ti-processor-sdk-rtos-k2hk-evm-02.00.01.07-Windows-x86-Install.exe. Then I loaded the serdes_diag_prbs_K2KC66ExampleProject.
    Enabled the #define serdes_diag_test_phy_type TEST_SERDES_PCIe in serdes_diag_platform.h, and try to do the Serdes_Example_PRBSTest. When I run the test in k2k board. there is no PRBS signal come out. I test the clock, clock is working in 100MB

    when i build the project , there is no error and serdes_diag_prbs_K2KC66ExampleProject.out is generated. But when i run the project,
    the information as below:
    -------------begin-----------------------
    [C66xx_0] Turning off L1 Data Cache. Turning off L2 Cache. Invalid Serdes Common Init
    --------------end------------------------
    CSL_SerdesLaneEnable(&serdes_lane_enable_params);
    has the error as below:
    --------------------begin----------------------------
    error:cannot load from non-primitive location
    ---------------------end---------------------------
    I checked the header files ,there are all right. what is the problem ?
    Thanks in advcance
    BRs
    WeiWang
  • Hello

    according to
    e2e.ti.com/.../11696.aspx

    It is only an issue with the display in the Expressions view and should not be an indication of any problems with the execution of the code itself.

    So I run the code, but the code go into an infinite loop in "lane_retval = CSL_SerdesLaneEnable(&serdes_lane_enable_params)" function.
    it check the status of lanes continuesly in function "CSL_SerdesGetStatus" by following code:
    ============================================================================
    retval &= (CSL_SERDES_STATUS)CSL_FEXTR(*(volatile uint32_t *)(base_addr + 0x1ff4), (0 + lane_num), (0 + lane_num));
    ========================================================================================
    but never get the right return value.

    I'm using pdk_k2hk_4_0_0 's serdes_diag_prbs_K2KC66ExampleProject code. Is this code support SERDES PCIE prbs test ?

    Thanks
    WeiWang
  • Hi,

    I tested a setup K2H EVM----- CI2V BOC for PCIE — K2H EVM with the latest Processor SDK 3.3 (PDK_K2HK_4.0.5), the program is serdes_diag_prbs_K2KC66ExampleProject.out using DSS script to drive the test as in user guide:
    ......
    66xx_0: GEL Output: (8d/e) Delay...
    C66xx_0: GEL Output: (10) Delay...
    C66xx_0: GEL Output: (12) Delay...
    C66xx_0: GEL Output: (13) SECCTL = 0x00090000
    C66xx_0: GEL Output: (Delay...
    C66xx_0: GEL Output: (Delay...
    C66xx_0: GEL Output: (14) PLLCTL = 0x00000041
    C66xx_0: GEL Output: PLL has been configured (CLKIN * PLLM / PLLD / PLLOD = PLLO
    UT):
    C66xx_0: GEL Output: PLL has been configured (122.879997 MHz * 625 / 32 / 2 = 12
    00.0 MHz)
    DSS: Serdes PRBS testing...
    DSS: Loading DSP program to 1st Keystone2 DSP core...
    DSS: Done!
    DSS: Loading DSP program to 2nd Keystone2 DSP core...
    DSS: Done!
    DSS: Removed all breakpoints on 1st Keystone2 DSPs...
    DSS: Removed all breakpoints on 2nd Keystone2 DSPs...
    DSS: Executing program on 2nd Keystone2 DSPs...
    DSS: Executing program on 1st Keystone2 DSPs...
    DSS: Execution started...
    Turning off L1 Data Cache.
    Turning off L1 Data Cache.
    Turning off L2 Cache.
    Turning off L2 Cache.
    Serdes Common Init Complete
    Serdes Common Init Complete
    Serdes Lane 0 Init Complete
    Serdes Lane 0 Init Complete
    Serdes Lane 1 Init Complete
    Serdes Lane 1 Init Complete
    Serdes Init Complete
    Serdes Init Complete
    Enabling TX PRBS Pattern
    Enabling TX PRBS Pattern
    att = 563224446 for lane 0 boost = 218938456 for lane 0
    att = -1977087799 for lane 1 boost = -222935804 for lane 1
    Lane 0 PRBS check timeout .........
    PRBS Scans complete!
    Lane 1 PRBS check timeout .........
    dss_test_complete_flag_device0: 0x5A5A5A5A
    dss_test_complete_flag_device1: 0xA5A5A5A5
    att = 1958382479 for lane 0 boost = 392658851 for lane 0
    att = 1640920731 for lane 1 boost = -835385668 for lane 1
    PRBS Scans complete!
    Serdes Diag Test Complete
    C:\ti\pdk_k2hk_4_0_5\packages\ti\diag\serdes_diag>

    I noticed that Rx signal validation timeout resulting in garbage RX ATT/BOOST. Probably the PRBS pattern has never been transmitted out. I opened a ticket for this.

    Regards, Eric