Hi
Is sprugs6d.pdf the serdes pcie's specifaction document?
When I try to check the init code in csl_wiz8_sb_refclk100MHz_pci_5Gbps function.
I find the meaning of registers are not match.
for example
CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0000),15, 8, (uint32_t)0x08);
CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0060), 7, 0, (uint32_t)0x5c);
CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0060),15, 8, (uint32_t)0x1c);
CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0060),23,16, (uint32_t)0x04);
CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0064),15, 8, (uint32_t)0xc7);
CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0064),23,16, (uint32_t)0x43);
CSL_FINSR(*(volatile uint32_t *)(base_addr + 0x0064),31,24, (uint32_t)0x03);
base_addr is 0x2320000
I can't find register "base_addr + 0x0060". And "base_addr + 0x0064" 's reigster , from bit 2~31 are reserved according to sprugs6d.pdf.
could you tell me why? or i'm checking the wrong specifiction ?
Thanks