Hello,
I have been working through the device clock tree and have noted some things that are puzzling to me. In setting up the NSS clocks, I have set the NSS PLL to 1GHz to give the following clocks:
Divider_NSS_PLL_1_RGMII_MHZ_250_CLK = 250 MHZ
Divider_NSS_PLL_0_RGMII_MHZ_5_CLK = 5 MHZ
Divider_NSS_PLL_2_GMII__RFTCLK = 125 MHZ
Divider_NSS_PLL_3_RGMII_MHZ_50_CLK = 50 MHZ
VCLK = 200 MHZ
ESW_CLK = 200 MHZ
SYSCLK1 = 600 MHZ
This all seems correct to me. The part that becomes confusing is the routing of the clock to the RMII_CLKOUT pin. In the TRM, Section 5.4.3, it is said that the clock can be sourced such that it is a 25MHz clock or a 50MHz clock. In the CTT, this pin is routed such that there are two available signals, a clock, and a copy of this clock divided by two. The trouble is, this clock, as indicated in the CTT, is the Divider_NSS_PLL_0_RGMII_MHZ_5_CLK, which is 5MHz. This seems incorrect. Should it be the case that the clock connected to this pin is Divider_NSS_PLL_3_RGMII_MHZ_50_CLK instead? This is the way that Figure 11-906 in the TRM shows the routing to be.
Jeff
