TMS320C6657: DDR ECC function verify failed.

Hi Denny,

I've notified the sw team. Their feedback will be posted here.

Best Regards,
Yordan

Denny,

Leveling errors and ECC configuration in KeyStone-I are completely independent.  You need to follow the sequence discussed in the Initialization Guide using the rules and tools provided.  These fully support C665x devices.  The documentation recommends use of Partial Automatic Leveling.  This is also the solution provided in all of the sample code and scripts provided.  Do not proceed with ECC testing until you have successfully validated the DDR3 implementation on your target board.  Be sure to complete the required length matching exercise and to then properly populate the PHY_CALC and REG_CALC worksheets.

Tom

Tom,

The same initial parameters of leveling. If no ECC enabled it can pass the leveling, if enable ecc it can't pass the leveling.

Do you have any suggestion about this? thanks!

BR,
Denny 

Tom,

I think this may not the leveling issue.
Ignore the leveling error. I just check the DDR ECC ranged address, it read write check failed.
If I check the address which is not in the range to ECC address, read and write ddr is fine.

BR,
Denny

I just set all the leveling parameters to 0, it's the same.
If I disable ecc function base on this parameters it can pass the leveling function, enable ecc function it can't pass.
Read write check ecc ranged address failed, not ecc ranged address success.

gpBootCfgRegs->DDR3_CONFIG_REG[2] = 0;
gpBootCfgRegs->DDR3_CONFIG_REG[3] = 0;
gpBootCfgRegs->DDR3_CONFIG_REG[4] = 0;
gpBootCfgRegs->DDR3_CONFIG_REG[5] = 0;
gpBootCfgRegs->DDR3_CONFIG_REG[6] = 0;
gpBootCfgRegs->DDR3_CONFIG_REG[7] = 0;
gpBootCfgRegs->DDR3_CONFIG_REG[8] = 0;
gpBootCfgRegs->DDR3_CONFIG_REG[9] = 0;
gpBootCfgRegs->DDR3_CONFIG_REG[10] = 0;

/*GTLVL_INIT_RATIO*/
gpBootCfgRegs->DDR3_CONFIG_REG[14] = 0;
gpBootCfgRegs->DDR3_CONFIG_REG[15] = 0;
gpBootCfgRegs->DDR3_CONFIG_REG[16] = 0;
gpBootCfgRegs->DDR3_CONFIG_REG[17] = 0;
gpBootCfgRegs->DDR3_CONFIG_REG[18] = 0;
gpBootCfgRegs->DDR3_CONFIG_REG[19] = 0;
gpBootCfgRegs->DDR3_CONFIG_REG[20] = 0;
gpBootCfgRegs->DDR3_CONFIG_REG[21] = 0;
gpBootCfgRegs->DDR3_CONFIG_REG[22] = 0;

Denny,

You are continuing to mix leveling and ECC.  Disable all ECC and verify that all memory can be written and read robustly.  Then we can talk about ECC.

Please provide a length match report showing that all 5 byte lanes and the fly-by nets are properly routed and verified.  Also, please provide your fully populated PHY_CALC and REG_CALC worksheets.

Is the DDR3 memory implemented using three x16 devices or five x8 devices?  Please provide the SDRAM part number.

Tom

Hi，Tom

We use three x16 devices,type is MT41K128M16JT-125ITK， SDRAM Datasheet and PHY_CALC and REG_CALC worksheets is added by the attachment.DDR3 PHY Calc v10.xlsx8182.DDR3 Register Calc v4.xlsxMT41K128M16JT-125ITK.pdf

Ray,

I still need to receive the length matching report.

Tom

Ray,

I also see that you are using an old version of the PHY_CALC worksheet.  Please download the latest version of KeyStone I DDR3 Initialization Application Report (SPRABL2E) and its associated spreadsheets.  You will see that you are not using the correct byte lanes for C665x.  This is also discussed in detail in the revised document.  Please correct the code and see if this resolves the issue.

Tom

Tom,

Could you explain what is " length matching report"? thanks very much!

BR,
Denny

Denny,

The DDR3 Design Requirements for KeyStone Devices Application Report (SPRABI1) provides requirements for matching the length of the fly-by nets from controller to each SDRAM and for data group nets to be matched from the controller to each SDRAM.  This is mandatory for robust DDR3 operation.  To validate these rules are met, you would need to either generate a table by hand or use the PCB layout tool to generate one.  Please see the attached report that was generated by Cadence Allegro.  Spreadsheet calculations were added to the last column to highlight the margin and any failing routes.  Please provide a report like this for the board that is being tested.

Tom

Example DDR3 Length match Report.xls

Tom，

I have used the latest version PHY_CALC worksheet and correct my code,the problem still exists。

1、enable ecc，ddr write/read test failed.
2、disable ecc，ddr write/read test successed.
I think that  after enable ecc,the ddr-ecc chip may have some effect on the other  ddr chip.

My question:
How to confirm the ddr-ecc chip is ok,when the ecc is disabled.

Ray

4745.DDR3 PHY Calc v11.xlsx

Ray,

Did you perform dummy writes to the entire ECC range before you started using it?  This is need to initialize the ECC content.

Tom

Tom,

The problem is after enable ECC, it can't pass the leveling. So it can't read/write DDR right. Can't do right dummy writes.

Also the same test code can run well on TCI6614 EVM board.

Do you have any idea about how to verify the ECC DDR CHIP? thanks!

BR,
Denny

Denny,

I am still waiting to see a length matching report.  This is a critical part of layout validation.  If length matching was not done correctly, the ECC discussion is a waste of time.

Tom

Tom,

Here is the  length matching report.

Ray

DDR3 Length match Report.xls

Ray,

The length report shows that the routing rules were not followed for the fly-by groups (address, command, control and clock). There is also a significant data discrepancy.  The clock is a very significant signal and it is not routed differentially.  You need to correct your board layout before we can help with this.

Tom

Hi Denny
I see that the internal update shows that you have used the same software and validated DDR ECC working on the c6657 EVM.

It does appear from the last comments from Tom that the board has significant violations on the DDR layout , that need to be corrected. While there is no easy way to confirm that the issues the customer is seeing is due to these violations, it cannot be ruled as a potential cause for the failures and in general such violations can impact any meaningful debug.

I have a few follow up questions
1) There is a request on this thread from Tom asking to confirm that all leveling and robustness tests work as expected if DDR ECC was not enabled - can you double confirm this to be the case?
2) You have another thread that has a MSMC ECC failure issue - is this failure seen on the same design or is this a new design? If so, how many boards tested and how many failing?
3) Is this a time 0 failure or field reported failures?
4) Do you see any difference in failures , if the DDR clock frequency was reduced?


Regards
Mukul

Hi Mukul,

About your questions:

1, Yes, Without DDR ecc enable all the leveling and robustness test work as expected. This product has MP more than 1 year, everything works fine.

2, About MSMC ECC issue, it's the same design now new one. Customer only catch one error in several hundreds products.

3, MSMC ecc issue is field report failures.

4, We don't see anything difference when ddr ecc failures. They have reduce the clock to 400MHZ, it's same.

Customer hope to make a new design to fix the ddr ecc issue, but they concerns:

1, They don't know what the root cause of this issue.

2,They don't know how to improve their design.

Could you please help about this? thanks!

BR,
Denny

Hi Denny
Thanks.
Just to further clarify , it appears to me that while it is the same design, customer is trying to enable DDR ECC for the first time and in doing so they are seeing all tested boards show failures when ECC is enableded? Correct?

Can they try lower than 400 MHz?

>>They don't know how to improve their design.

Did you share recommendations that Tom provided on the violations they have based on the length matching report assessment? Are they planning to address this in their design ?

Denny,

We already established that the DDR3 routing rules were not followed.  The rules for matching the lengths per signal groups and differential routing for pairs like DQS and CLK and proper trace spacing are all critical to robust DDR operation.  There are multiple documents that must be reviewed that contain the required information.  The following E2E link lists out the steps for designing and commissioning a DDR3 layout: e2e.ti.com/.../462229

Tom