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CCS/TMS320C6678: SRIO connected to FPGA error

YUCHAO WANG
Expert 1265 points
Part Number: TMS320C6678

Tool/software: Code Composer Studio

Hi TI engineer

We use C6678 connected to Xlinix Virtex-7 in our application. The connection is 4x , 5.0G
Baud per lane.The reference clock of C6678 SRIO is 156.25MHz, for FPGA it is 125MHz

But we met some problem in our use. It is described as follows:

1. After initialize, the register shows that only 1x is linked. The value of register
0x0290b15c is 0xC0600001, It should be 0xD0600001 as normal;
2. When C6678 send data to FPGA for the first time, it can't be received immediately(For
we have a loopback test here, if Fpga receive the data , it will send back to C6678). During this
occurs, C6678 will get the response data from Fpga 10 seconds later.The data is 64KB;

3.The transfer after then seems OK.Only first transfer is abnormal.

4.We try to initialize srio again when found 0x0290b15c is 0xc0600001. After initialize
for the 2nd time, the value of the regs changes to 0xd0600001, but it didn;t recover really. For the
first transfer is still abnormal.

5. This error doesn't happen very often, it is nearly 1times between hundreds of Power
on.

Someone said the error is because the reference clock of C6678 and FPGA is not the same.Do
you agree it? Could you give us some advice about this?Thank you very much.

Regards,Yuchao

  • 0
    TI__Guru 65405 points
    I've forwarded your query to the design experts. Their feedback should be posted here.

    BR
    Tsvetolin Shulev
  • 0 in reply to Cvetolin Shulev-XID
    TI__Mastermind 43296 points
    Hi Yuchao,

    156.25MHz is a supported reference clock for SRIO running at 5G baud rate. As noted in SRIO UG, the Physical layer SerDes has a built-in PLL. This reference clock has no timing relationship to the serial data and is asynchronous to any CPU system clock.

    One thought is the Serdes tuning, see the document "SERDES Link Commissioning on KeyStone I and II Devices" www.ti.com/litv/pdf/sprac37 and discussion in other thread: e2e.ti.com/.../1111108

    Does the FPGA support BER testing using PRBS pattern?

    Regards,
    Garrett
  • 0 in reply to Garrett Ding
    Expert 1265 points
    Hi Ding
    About the Serdes tuning, I only find this:
    "There are customer board designs involved in interconnection between the Keystone II and Keystone I
    devices. SRIO, SGMII, 10GbE and PCIE are industry standards and typically there are switches available
    for inter-connection. However, Hyperlink is a TI standard and there have been some designs that
    Keystone II devices directly connected to Keystone I devices via separate Hyperlink ports. There is a need
    for Hyperlink SerDes tuning for this scenario.
    For the Keystone I devices, the MCSDK/Processor SDK packages do not provide any SerDes tuning
    tools. The SerDes bit error counter is not chip-level MMR, thus it can not be accessed by a DSP program.
    TI does not support any tools to access the SerDes error counter in Keystone I device. In such a case, the
    Hyperlink block error counter can be used as an indicator to tune the SerDes parameters."
    Do you mean that during the error occurs I can check the hyperlink serdes regs to know the state?But it seems hyplnk worked well?
    I can't tell if FPGA could do it.I need to verify it with our FPGA developers.Do you think it can help us to address the problem?
    Thank you for your help
  • 0 in reply to YUCHAO WANG
    TI__Mastermind 43296 points
    Yuchao,

    It's true that "For the Keystone I devices, the MCSDK/Processor SDK packages do not provide any SerDes tuning
    tools." and you probably have to develop a mechanism to collect BER rate from FPGA for the Tx path. Alternatively, refer to section 1.2 keystone I Devvice SerDes Tx Tunning - The SRIO and Hyperlink transmitters...Simulation of the target PCB platform with appropriate 3D EM modeling and the KeyStone I IBIS-AMI SerDes models is the best method of creating initial starting values for the actual PCB.

    Regards, Garrett