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66ak2l06: 66ak2l06 jesd 120mhz rate needed instead of the 122.88 or 153.6 default rates

bryan ogilvie
Intellectual 350 points
Part Number: 66AK2L06
Other Parts Discussed in Thread: RFSDK,

Hello again,

I am planning on running our JESD interface at 120MHZ which is different than the 122.88MHZ or 153.6MHZ that is listed in the

Recommended SerDes Register Configuration Options 6.3.  the note below the table says

"TI requires customers to use TI-generated and supported, default PHY configurations for all

operating modes (supplied as part of MCSDK). TI cannot directly support customer

generated configuration files. The code/registers used and accessed in these configurations

must be considered as the "default" for a given interface use-case and must not be modified

by a customer."

Will I be able to correctly modify the JESD to use our 120MHZ reference and still use the MCSDK to do this?  What code/registers will need to be changed from the "default" use case to accommodate the 120MHZ sampling rate?

thanks -b

  • 0
    TI__Guru**** 161600 points
    Hi,

    I've notified the factory team. Their feedback will be posted here.

    Best Regards,
    Yordan
  • 0 in reply to Yordan Kovachev
    TI__Mastermind 37500 points
    Hello,
    There are several sections that need to be modified, none of these are released with RFSDK, you would need to engage the third party custom development with CommAgility - England, or Azcom - Italy. The short answer is its not in the RFSDK. The sections that need modification are:
    a) The DFE clock rate takes input 122.88Mhz and develops with DFE PLL for (PLL clk)/[logic clk]
    122.88e6 in -> (245.76*4) / 245.76Mhz or (368.64 * 2) / 368.64Mhz - DFE and IQN clock
    b) The serdes PLL needs to generate a multiple of the IQ rate in DFE
    IQrate * 10bits/byte * 2 bytes per I or Q * (parallel IQ x1, interleaved IQ x2, TDM interleaved IQ x4)
    the serdes configurations are in the MCSDK these are the IQ Msps rates 61.44, 92.16,122.88, 184.32, 245.76, 368.64
    c) JESD SYSREF - is normally based on 122.88Msps, for other than Type 0.

    In order to use 120Mhz, you would take the 66ak2l06 EVM, the DLC card (which the developer's should have) and the appropriate DAC, ADC card.
    The first part is a digital loopback, and includes PLL and clocks internal to DFE and IQN,
    1) PLL limitations can be checked by third party developer, PLL User guide
    2) Serdes multiplier PLL, is not done by the developer, TI has to be involved, and currently these are not changed from the rates above( they
    are in the MCSDK for TypeA serdes. This may be a more limiting requirement
    3) JESD SYSREF if its type 0, then the SYSREF is not required. If its type 1 that is different.

    Regards,
    Joe Quintal