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TMS320C6678: About C66x Corepac L2 EDC function

Allen35065
Expert 3225 points
Part Number: TMS320C6678

Hi expert,

From Corepac user guide, the action of EDC function of L2 is different on L1P and L1D read.

1. Error Detection is performed on all L2 data fetches by L1D cache without any correction.

2. The L2 memory controller always performs a full hamming code check on 128-bit reads of L2 regardless of whether the fetch is from L1P, L1D, IDMA, or DMA.

Could you please tell me the reason we only detect error on L1D access but not correction?

Thanks.

Allen

  • 0
    TI__Guru**** 161600 points

    Hi,

    I've notified the factory team. Their feedback will be posted here.

    Best Regards,
    Yordan

  • 0 in reply to Yordan Kovachev
    TI__Guru* 95265 points
    Hi,

    For C66x, the primary purpose of EDC feature is to protect the program code and static data which are not frequently changed.

    L1P only has error detection, but not correction. When error is detected in L1P cache, the DSP needs to
    invalidate program code by flushing the content of the L1P Cache.

    L2 EDC logic can detect double-bit errors and correct single-bit errors.

    I noticed: Error Detection is performed on all L2 data fetches by L1D cache without any correction in section 11.3 of the corepac user guide, I am looking for more explanation of this.

    Regards, Eric
  • 0 in reply to lding
    TI__Expert 3225 points
    Hi Eric,

    Do you have any information about this L1D cache EDC question?

    Thanks.
    Allen